From patchwork Thu Jun 26 15:18:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 32569 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yk0-f198.google.com (mail-yk0-f198.google.com [209.85.160.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 33286201EF for ; Thu, 26 Jun 2014 15:21:50 +0000 (UTC) Received: by mail-yk0-f198.google.com with SMTP id 9sf5207996ykp.1 for ; Thu, 26 Jun 2014 08:21:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:content-type:content-transfer-encoding; bh=brDjhJDBRfrQSPD14A5YtKH2AEsfpCdP0sy119QEgxQ=; b=BzjDQtHAqAxOtlUF4+IwLirMObcXrpcF9cfb7aSVOlhfvNBzNOS/G37rwCn1zUteEq EtdT9Gsu+xUgkhcyJgu5OAPbgYYpPPMzb49cqfVWs/JKH/huk9wWcJIj23gRBgjzSK4K vipeTblwo+4Dh5qirAXnXs2KTOrSf7GYqhaXMxzXi83kyKZPx982+WlDD6KNrXYONbl4 U3EzM8ExPavSAIVT2zenERbcfelTyeVDjO15KL9MMt/JeZLoQmFYf+Crkvv0NJrhFU05 g6DUiF0F/IFRo/00NORtYnwh57vOVy8qRzTmapo442LTqdJO7qxdBmixiwwCj9yvH9go W4UA== X-Gm-Message-State: ALoCoQnf5dsnIXmvnEIV430xzh6mINLP42rSUZjWlmFWaHarn51cSQbTUBPKDX0B5SOO/jd1fMPy X-Received: by 10.58.187.68 with SMTP id fq4mr8747201vec.0.1403796109931; Thu, 26 Jun 2014 08:21:49 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.30.36 with SMTP id c33ls170854qgc.72.gmail; Thu, 26 Jun 2014 08:21:49 -0700 (PDT) X-Received: by 10.58.48.193 with SMTP id o1mr1269998ven.68.1403796109864; Thu, 26 Jun 2014 08:21:49 -0700 (PDT) Received: from mail-ve0-f172.google.com (mail-ve0-f172.google.com [209.85.128.172]) by mx.google.com with ESMTPS id jo10si4649714veb.21.2014.06.26.08.21.49 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Jun 2014 08:21:49 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) client-ip=209.85.128.172; Received: by mail-ve0-f172.google.com with SMTP id jz11so3860841veb.31 for ; Thu, 26 Jun 2014 08:21:49 -0700 (PDT) X-Received: by 10.52.88.44 with SMTP id bd12mr1033153vdb.86.1403796109660; Thu, 26 Jun 2014 08:21:49 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp38122vcb; Thu, 26 Jun 2014 08:21:49 -0700 (PDT) X-Received: by 10.66.146.72 with SMTP id ta8mr21969701pab.150.1403796108929; Thu, 26 Jun 2014 08:21:48 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id dn8si10288046pac.129.2014.06.26.08.21.48 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Jun 2014 08:21:48 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X0BTO-0006rm-FZ; Thu, 26 Jun 2014 15:20:26 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X0BT2-0005R1-VV for linux-arm-kernel@lists.infradead.org; Thu, 26 Jun 2014 15:20:06 +0000 Received: from leverpostej.cambridge.arm.com (leverpostej.cambridge.arm.com [10.1.205.151]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id s5QFInws014784; Thu, 26 Jun 2014 16:19:41 +0100 (BST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv3 4/5] arm64: cachetype: report weakest cache policy Date: Thu, 26 Jun 2014 16:18:45 +0100 Message-Id: <1403795926-17139-5-git-send-email-mark.rutland@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1403795926-17139-1-git-send-email-mark.rutland@arm.com> References: <1403795926-17139-1-git-send-email-mark.rutland@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140626_082005_425978_2F81E5B9 X-CRM114-Status: GOOD ( 14.94 ) X-Spam-Score: -5.0 (-----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-5.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.96.50 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record Cc: Mark Rutland , catalin.marinas@arm.com, lorenzo.pieralisi@arm.com, will.deacon@arm.com, ard.biesheuvel@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mark.rutland@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 In big.LITTLE systems, the I-cache policy may differ across CPUs, and thus we must always meet the most stringent maintenance requirements of any I-cache in the system when performing maintenance to ensure correctness. Unfortunately this requirement is not met as we always look at the current CPU's cache type register to determine the maintenance requirements. This patch causes the I-cache policy of all CPUs to be taken into account for icache_is_aliasing and icache_is_aivivt. If any I-cache in the system is aliasing or AIVIVT, the respective function will return true. At boot each CPU may set flags to identify that at least one I-cache in the system is aliasing and/or AIVIVT. The now unused and potentially misleading icache_policy function is removed. Signed-off-by: Mark Rutland Acked-by: Will Deacon --- arch/arm64/include/asm/cachetype.h | 16 ++++++++++------ arch/arm64/kernel/cpuinfo.c | 32 +++++++++++++++++++++++++++++--- 2 files changed, 39 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h index 4b23e75..7a2e076 100644 --- a/arch/arm64/include/asm/cachetype.h +++ b/arch/arm64/include/asm/cachetype.h @@ -30,10 +30,14 @@ #ifndef __ASSEMBLY__ -static inline u32 icache_policy(void) -{ - return (read_cpuid_cachetype() >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK; -} +#include + +#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) + +#define ICACHEF_ALIASING BIT(0) +#define ICACHEF_AIVIVT BIT(1) + +extern unsigned long __icache_flags; /* * Whilst the D-side always behaves as PIPT on AArch64, aliasing is @@ -41,12 +45,12 @@ static inline u32 icache_policy(void) */ static inline int icache_is_aliasing(void) { - return icache_policy() != ICACHE_POLICY_PIPT; + return test_bit(ICACHEF_ALIASING, &__icache_flags); } static inline int icache_is_aivivt(void) { - return icache_policy() == ICACHE_POLICY_AIVIVT; + return test_bit(ICACHEF_AIVIVT, &__icache_flags); } static inline u32 cache_type_cwg(void) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 65907f3..20ca6d0 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -19,7 +19,9 @@ #include #include +#include #include +#include #include /* @@ -30,7 +32,29 @@ DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); static struct cpuinfo_arm64 boot_cpu_data; -static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) +static char *icache_policy_str[] = { + [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", + [ICACHE_POLICY_AIVIVT] = "AIVIVT", + [ICACHE_POLICY_VIPT] = "VIPT", + [ICACHE_POLICY_PIPT] = "PIPT", +}; + +unsigned long __icache_flags; + +static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info, + unsigned int cpu) +{ + u32 l1ip = CTR_L1IP(info->reg_ctr); + + if (l1ip != ICACHE_POLICY_PIPT) + set_bit(ICACHEF_ALIASING, &__icache_flags); + if (l1ip == ICACHE_POLICY_AIVIVT); + set_bit(ICACHEF_AIVIVT, &__icache_flags); + + pr_info("Detected %s I-cache on CPU%d", icache_policy_str[l1ip], cpu); +} + +static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info, unsigned int cpu) { info->reg_cntfrq = arch_timer_get_cntfrq(); info->reg_ctr = read_cpuid_cachetype(); @@ -56,20 +80,22 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); + + cpuinfo_detect_icache_policy(info, cpu); } void cpuinfo_store_cpu(void) { unsigned int cpu = smp_processor_id(); struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); - __cpuinfo_store_cpu(info); + __cpuinfo_store_cpu(info, cpu); } void __init cpuinfo_store_boot_cpu(void) { unsigned int cpu = smp_processor_id(); struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); - __cpuinfo_store_cpu(info); + __cpuinfo_store_cpu(info, cpu); boot_cpu_data = *info; }