From patchwork Wed Jun 25 09:28:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 32469 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pb0-f71.google.com (mail-pb0-f71.google.com [209.85.160.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id AD01120C88 for ; Wed, 25 Jun 2014 09:31:41 +0000 (UTC) Received: by mail-pb0-f71.google.com with SMTP id rq2sf6190932pbb.6 for ; Wed, 25 Jun 2014 02:31:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:content-type:content-transfer-encoding; bh=cBefIBgIyO8FSb4Jl7dW6W2cy8Zsgq7IqcxMaDgAkeM=; b=hg69k9nIClwM0mLHs2dLW4wS5zTEtBLr0PU8blqfyumPKYucwq5FozTAZKlmn70MH+ 3S8V581EZLrOaPRa+J+WAX2lYndrQknlWx8WSsKhGF960E8mS0fESmJS/eZoH69/aLC4 APvqJNfnsHCvMOysTjloWz+W9z+jPGCZV+g3ozD47WMmWsrUsvxkzvWTYozTBr938PPr gZNBZaOqbzHAQiAMIzUOShxZVhXQ7Ov7gP41Ub5MifpfJngTZZDBh+/hoJeCFSk2LTcG sOOILQJ/btjubub/GekzVg9rrzJxpV7P9473A7R4AW/Ji0juI1ZCk58qENzgFbcr6Nb8 oAPw== X-Gm-Message-State: ALoCoQlL+90rZbF9A3iYZPMspcqcPt+m6mpkUYfjEoG2ymvEehVOeoli/C2gUop5nwdwycOaUp7v X-Received: by 10.66.169.231 with SMTP id ah7mr3707557pac.40.1403688701011; Wed, 25 Jun 2014 02:31:41 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.28.67 with SMTP id 61ls853527qgy.20.gmail; Wed, 25 Jun 2014 02:31:40 -0700 (PDT) X-Received: by 10.220.15.8 with SMTP id i8mr48220vca.45.1403688700911; Wed, 25 Jun 2014 02:31:40 -0700 (PDT) Received: from mail-vc0-f172.google.com (mail-vc0-f172.google.com [209.85.220.172]) by mx.google.com with ESMTPS id kk9si1886481vdb.77.2014.06.25.02.31.40 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 25 Jun 2014 02:31:40 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) client-ip=209.85.220.172; Received: by mail-vc0-f172.google.com with SMTP id hy10so1593297vcb.17 for ; Wed, 25 Jun 2014 02:31:40 -0700 (PDT) X-Received: by 10.220.92.135 with SMTP id r7mr5852890vcm.11.1403688700827; Wed, 25 Jun 2014 02:31:40 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp274532vcb; Wed, 25 Jun 2014 02:31:40 -0700 (PDT) X-Received: by 10.140.51.37 with SMTP id t34mr9267300qga.50.1403688700263; Wed, 25 Jun 2014 02:31:40 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id b47si3781795qga.51.2014.06.25.02.31.40 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Jun 2014 02:31:40 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WzjX8-0005x6-94; Wed, 25 Jun 2014 09:30:26 +0000 Received: from fw-tnat.austin.arm.com ([217.140.110.23] helo=collaborate-mta1.arm.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WzjWN-0004Jw-V2 for linux-arm-kernel@lists.infradead.org; Wed, 25 Jun 2014 09:29:40 +0000 Received: from e102391-lin.cambridge.arm.com (e102391-lin.cambridge.arm.com [10.1.209.143]) by collaborate-mta1.arm.com (Postfix) with ESMTP id EC7DA13FAC3; Wed, 25 Jun 2014 04:28:57 -0500 (CDT) From: Marc Zyngier To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 5/9] irqchip: GICv3: Convert to EOImode == 1 Date: Wed, 25 Jun 2014 10:28:46 +0100 Message-Id: <1403688530-23273-6-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1403688530-23273-1-git-send-email-marc.zyngier@arm.com> References: <1403688530-23273-1-git-send-email-marc.zyngier@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140625_022940_148151_32B0D7CD X-CRM114-Status: GOOD ( 14.09 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record Cc: Catalin Marinas , Thomas Gleixner , Will Deacon , Christoffer Dall , eric.auger@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: marc.zyngier@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 So far, GICv3 has been used in with EOImode == 0. The effect of this mode is to perform the priority drop and the deactivation of the interrupt at the same time. While this works perfectly for Linux (we only have a single priority), it causes issues when an interrupt is forwarded to a guest, and when we want the guest to perform the EOI itself. For this case, the GIC architecture provides EOImode == 1, where: - A write to ICC_EOIR1_EL1 drops the priority of the interrupt and leaves it active. Other interrupts at the same priority level can now be taken, but the active interrupt cannot be taken again - A write to ICC_DIR_EL1 marks the interrupt as inactive, meaning it can now be taken again. This patch converts the driver to this new mode, without any other feature. Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 1 + drivers/irqchip/irq-gic-v3.c | 6 ++++-- include/linux/irqchip/arm-gic-v3.h | 7 +++++++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 822f55e..922f228 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -616,6 +616,7 @@ static void its_unmask_irq(struct irq_data *d) static void its_eoi_irq(struct irq_data *d) { gic_write_eoir(d->hwirq); + gic_write_dir(d->hwirq); } static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 3ae53c1..26a08ce 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -238,6 +238,7 @@ static void gic_unmask_irq(struct irq_data *d) static void gic_eoi_irq(struct irq_data *d) { gic_write_eoir(gic_irq(d)); + gic_write_dir(gic_irq(d)); } static int gic_set_type(struct irq_data *d, unsigned int type) @@ -297,6 +298,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs } if (irqnr < 16) { gic_write_eoir(irqnr); + gic_write_dir(irqnr); #ifdef CONFIG_SMP handle_IPI(irqnr, regs); #else @@ -400,8 +402,8 @@ static void gic_cpu_sys_reg_init(void) /* Set priority mask register */ gic_write_pmr(DEFAULT_PMR_VALUE); - /* EOI deactivates interrupt too (mode 0) */ - gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); + /* EOI drops priority only (mode 1) */ + gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); /* ... and let's hit the road... */ gic_write_grpen1(1); diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 023b49d..a0bff2f 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -229,6 +229,7 @@ #define ICC_EOIR1_EL1 S3_0_C12_C12_1 #define ICC_IAR1_EL1 S3_0_C12_C12_0 +#define ICC_DIR_EL1 S3_0_C12_C11_1 #define ICC_SGI1R_EL1 S3_0_C12_C11_5 #define ICC_PMR_EL1 S3_0_C4_C6_0 #define ICC_CTLR_EL1 S3_0_C12_C12_4 @@ -303,6 +304,12 @@ static inline void gic_write_eoir(u64 irq) isb(); } +static inline void gic_write_dir(u64 irq) +{ + asm volatile("msr " __stringify(ICC_DIR_EL1) ", %0" : : "r" (irq)); + isb(); +} + int its_cpu_init(void); struct irq_chip *its_init(struct device_node *node, struct rdist *rdist, struct irq_domain *domain);