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[82.33.25.158]) by mx.google.com with ESMTPSA id hi2sm7881147wjb.29.2014.06.19.03.38.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jun 2014 03:38:53 -0700 (PDT) From: Daniel Thompson To: Jason Wessel Cc: Daniel Thompson , kgdb-bugreport@lists.sourceforge.net, patches@linaro.org, linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, linux-kernel@vger.kernel.org, John Stultz , Anton Vorontsov , Colin Cross , Dirk Behme , kernel-team@android.com, Russell King , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , "David A. Long" , Nicolas Pitre , Catalin Marinas , Frederic Weisbecker , Linus Walleij , Christoffer Dall , kernel@stlinux.com, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, Jason Cooper , Nicolas Pitre , Sricharan R Subject: [PATCH v4 04/13] irqchip: gic: Add support for FIQ management Date: Thu, 19 Jun 2014 11:38:14 +0100 Message-Id: <1403174303-25456-5-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1403174303-25456-1-git-send-email-daniel.thompson@linaro.org> References: <1401961994-18033-1-git-send-email-daniel.thompson@linaro.org> <1403174303-25456-1-git-send-email-daniel.thompson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.thompson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch introduces callbacks to route interrupts to or away from the FIQ signal and registers these callbacks with the FIQ infrastructure (if the device can supports it). Both these aspects combine and allow a driver to deploy a FIQ handler without any machine specific knowledge; it can be used effectively on multi-platform kernels. Signed-off-by: Daniel Thompson Cc: Thomas Gleixner Cc: Jason Cooper Cc: Nicolas Pitre Cc: Christoffer Dall Cc: Sricharan R --- drivers/irqchip/irq-gic.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index bbffca3..0300c08 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -366,6 +366,58 @@ static struct irq_chip gic_chip = { }; #ifdef CONFIG_FIQ +/* + * Shift an interrupt between Group 0 and Group 1. + * + * In addition to changing the group we also modify the priority to + * match what "ARM strongly recommends" for a system where no Group 1 + * interrupt must ever preempt a Group 0 interrupt. + */ +static void gic_set_group_irq(struct irq_data *d, int group) +{ + unsigned int grp_reg = gic_irq(d) / 32 * 4; + u32 grp_mask = 1 << (gic_irq(d) % 32); + u32 grp_val; + + unsigned int pri_reg = (gic_irq(d) / 4) * 4; + u32 pri_mask = 1 << (7 + ((gic_irq(d) % 4) * 8)); + u32 pri_val; + + raw_spin_lock(&irq_controller_lock); + + grp_val = readl_relaxed(gic_dist_base(d) + GIC_DIST_IGROUP + grp_reg); + pri_val = readl_relaxed(gic_dist_base(d) + GIC_DIST_PRI + pri_reg); + + if (group) { + grp_val |= grp_mask; + pri_val |= pri_mask; + } else { + grp_val &= ~grp_mask; + pri_val &= ~pri_mask; + } + + writel_relaxed(grp_val, gic_dist_base(d) + GIC_DIST_IGROUP + grp_reg); + writel_relaxed(pri_val, gic_dist_base(d) + GIC_DIST_PRI + pri_reg); + + raw_spin_unlock(&irq_controller_lock); +} + +static void gic_enable_fiq(struct irq_data *d) +{ + gic_set_group_irq(d, 0); +} + +static void gic_disable_fiq(struct irq_data *d) +{ + gic_set_group_irq(d, 1); +} + +static struct fiq_chip gic_fiq = { + .fiq_enable = gic_enable_fiq, + .fiq_disable = gic_disable_fiq, + .fiq_eoi = gic_eoi_irq, +}; + static void __init gic_init_fiq(struct gic_chip_data *gic, irq_hw_number_t first_irq, unsigned int num_irqs) @@ -394,6 +446,12 @@ static void __init gic_init_fiq(struct gic_chip_data *gic, if (!gic->fiq_enable) return; + + /* + * FIQ is supported on this device! Register our chip data. + */ + for (i = 0; i < num_irqs; i++) + fiq_register_mapping(first_irq + i, &gic_fiq); } #else /* CONFIG_FIQ */ static inline void gic_init_fiq(struct gic_chip_data *gic,