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[209.132.180.67]) by mx.google.com with ESMTP id xz3si17935440pab.175.2014.06.17.10.11.34; Tue, 17 Jun 2014 10:11:34 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934121AbaFQRLZ (ORCPT + 27 others); Tue, 17 Jun 2014 13:11:25 -0400 Received: from mail-wg0-f48.google.com ([74.125.82.48]:49102 "EHLO mail-wg0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933557AbaFQRLW (ORCPT ); Tue, 17 Jun 2014 13:11:22 -0400 Received: by mail-wg0-f48.google.com with SMTP id n12so7456676wgh.7 for ; Tue, 17 Jun 2014 10:11:21 -0700 (PDT) X-Received: by 10.194.110.10 with SMTP id hw10mr15777082wjb.81.1403025081314; Tue, 17 Jun 2014 10:11:21 -0700 (PDT) Received: from localhost.localdomain ([109.129.12.44]) by mx.google.com with ESMTPSA id w9sm42284051eev.4.2014.06.17.10.11.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Jun 2014 10:11:20 -0700 (PDT) From: Jean Pihet To: Will Deacon , linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, Sneha Priya , linux-kernel@vger.kernel.org Cc: Jean Pihet Subject: [PATCH] ARM: perf: allow tracing with kernel tracepoints events Date: Tue, 17 Jun 2014 19:11:05 +0200 Message-Id: <1403025065-18001-1-git-send-email-jean.pihet@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jean.pihet@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , When tracing with tracepoints events the IP and CPSR are set to 0, preventing the perf code to resolve the symbols: ./perf record -e kmem:kmalloc cal [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.007 MB perf.data (~321 samples) ] ./perf report Overhead Command Shared Object Symbol ........ ....... ............. ........... 40.78% cal [unknown] [.]00000000 31.6% cal [unknown] [.]00000000 The examination of the gathered samples (perf report -D) shows the IP is set to 0 and that the samples are considered as user space samples, while the IP should be set from the registers and the samples should be considered as kernel samples. The fix is to implement perf_arch_fetch_caller_regs for ARM, which fills the necessary registers used for the callchain unwinding and to determine the user/kernel space property of the samples: ip, sp, fp and cpsr. Tested with perf record and tracepoints filtering (-e ), with unwinding using fp (--call-graph fp) and dwarf info (--call-graph dwarf). Reported by Sneha Priya on linaro-dev, cf. http://lists.linaro.org/pipermail/linaro-dev/2014-May/017151.html Signed-off-by: Jean Pihet Cc: Will Deacon Reported-by: Sneha Priya --- arch/arm/include/asm/perf_event.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h index 7558775..5e31d46 100644 --- a/arch/arm/include/asm/perf_event.h +++ b/arch/arm/include/asm/perf_event.h @@ -26,6 +26,25 @@ struct pt_regs; extern unsigned long perf_instruction_pointer(struct pt_regs *regs); extern unsigned long perf_misc_flags(struct pt_regs *regs); #define perf_misc_flags(regs) perf_misc_flags(regs) + +/* + * Take a snapshot of the regs. + * We only need a few of the regs: + * - ip for PERF_SAMPLE_IP + * - sp, fp for callchains + * - cpsr for user_mode() tests + */ +#define perf_arch_fetch_caller_regs(regs, __ip) { \ + instruction_pointer(regs)= (__ip); \ + __asm__ ( \ + "mov %[_ARM_sp], sp \n\t" \ + "mov %[_ARM_fp], fp \n\t" \ + "mrs %[_ARM_cpsr], cpsr \n\t" \ + : [_ARM_sp] "=r" (regs->ARM_sp), \ + [_ARM_fp] "=r" (regs->ARM_fp), \ + [_ARM_cpsr] "=r" (regs->ARM_cpsr) \ + ); \ +} #endif #endif /* __ARM_PERF_EVENT_H__ */