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[2001:1868:205::9]) by mx.google.com with ESMTPS id r10si8295492qad.65.2014.06.05.06.40.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Jun 2014 06:40:34 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WsXt0-00071W-DL; Thu, 05 Jun 2014 13:39:18 +0000 Received: from szxga03-in.huawei.com ([119.145.14.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WsXsq-0006oy-4e for linux-arm-kernel@lists.infradead.org; Thu, 05 Jun 2014 13:39:09 +0000 Received: from 172.24.2.119 (EHLO szxeml211-edg.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id APP85431; Thu, 05 Jun 2014 21:38:10 +0800 (CST) Received: from SZXEML448-HUB.china.huawei.com (10.82.67.191) by szxeml211-edg.china.huawei.com (172.24.2.182) with Microsoft SMTP Server (TLS) id 14.3.158.1; Thu, 5 Jun 2014 21:38:09 +0800 Received: from localhost (10.177.27.142) by szxeml448-hub.china.huawei.com (10.82.67.191) with Microsoft SMTP Server id 14.3.158.1; Thu, 5 Jun 2014 21:38:00 +0800 From: Zhen Lei To: Catalin Marinas , Will Deacon , linux-arm-kernel Subject: [PATCH RFC v1 1/2] documentation/iommu: Add description of Hisilicon System MMU binding Date: Thu, 5 Jun 2014 21:37:09 +0800 Message-ID: <1401975430-2648-2-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.8.4.msysgit.0 In-Reply-To: <1401975430-2648-1-git-send-email-thunder.leizhen@huawei.com> References: <1401975430-2648-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.27.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140605_063908_720893_8BA675D4 X-CRM114-Status: GOOD ( 13.07 ) X-Spam-Score: -1.4 (-) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-1.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [119.145.14.66 listed in list.dnswl.org] -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record Cc: Xinwei Hu , Kefeng Wang , Zefan Li , Zhen Lei , Tianhong Ding X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: thunder.leizhen@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This patch adds a description of the device tree binding for the Hisilicon System MMU architecture. Signed-off-by: Zhen Lei --- .../devicetree/bindings/iommu/hisilicon,smmu.txt | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/hisilicon,smmu.txt -- 1.8.0 diff --git a/Documentation/devicetree/bindings/iommu/hisilicon,smmu.txt b/Documentation/devicetree/bindings/iommu/hisilicon,smmu.txt new file mode 100644 index 0000000..a2b2f23 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/hisilicon,smmu.txt @@ -0,0 +1,70 @@ +* Hisilicon System MMU Architecture Implementation + +Hisilicon SoCs may contain an implementation of the Hisilicon System Memory +Management Unit Architecture, which can be used to provide 1 or 2 stages +of address translation to bus masters external to the CPU. + +The SMMU may also raise interrupts in response to various fault +conditions. + +** System MMU required properties: + +- compatible : Should be one of: + + "hisilicon,smmu-v1" + + depending on the particular implementation and/or the + version of the architecture implemented. + +- reg : Base address and size of the SMMU. + +- #global-interrupts : The number of global interrupts exposed by the + device. + +- interrupts : Interrupt list, with the first #global-irqs entries + corresponding to the global interrupts and exactly one + following entry corresponding to context interrupt. + +- smmu-masters : A list of phandles to device nodes representing bus + masters for which the SMMU can provide a translation + and their corresponding StreamIDs (see example below). + +** System MMU optional properties: + +- smmu-cb-memtype : A list of StreamIDs which not translate address but + translate attributes. The StreamIDs list here can not be + used for map(translation) mode again. + StreamID first, then the type list below: + 1, cahceable, WBRAWA, Normal outer and inner write-back + 2, non-cacheable, Normal outer and inner non-cacheable + 3, device, nGnRE + others, bypass + +- smmu-bypass-vmid : Specify which context bank is used for bypass mode. + If omit, vmid=255 is default. + +Example: + + smmu { + compatible = "hisilicon,smmu-v1"; + reg = <0x40040000 0x1000>; + #global-interrupts = <1>; + + /* + * Global and context faults may use the same interrupt, if + * only one exist. + */ + interrupts = <0 188 4>, + <0 188 4>; /* The last is the context interrupt */ + + /* + * StreamID = 0 is bypass and force cacheable(WBRAWA). + */ + smmu-cb-memtype = <0x0 1>; + + /* + * Two DMA controllers, each with exactly one StreamID. + */ + smmu-masters = <&dma0 0x0001>, + <&dma1 0x0002>; + };