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[82.45.1.190]) by mx.google.com with ESMTPSA id s10sm4355698wjs.29.2014.06.04.09.31.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jun 2014 09:31:17 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chris@printf.net, ulf.hansson@linaro.org, maxime.coquelin@st.com, patrice.chotard@st.com, srinivas.kandagatla@gmail.com Cc: peter.griffin@linaro.org, kernel@stlinux.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Giuseppe Cavallaro Subject: [PATCH v3 05/10] ARM: STi: DT: Add sdhci pin configuration for stih415 Date: Wed, 4 Jun 2014 17:30:19 +0100 Message-Id: <1401899424-1365-6-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1401899424-1365-1-git-send-email-peter.griffin@linaro.org> References: <1401899424-1365-1-git-send-email-peter.griffin@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.griffin@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds the required pin config for the sdhci controller present in the stih415 SoC. Signed-off-by: Giuseppe Cavallaro Signed-off-by: Peter Griffin Acked-by: Lee Jones Acked-by: Maxime Coquelin --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index caeac7e..eee2373 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -429,6 +429,27 @@ }; }; }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&PIO14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&PIO14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&PIO14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&PIO14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&PIO15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&PIO15 3 ALT4 IN>; + data4 = <&PIO16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&PIO16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&PIO16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&PIO16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&PIO17 1 ALT4 OUT>; + cd = <&PIO17 2 ALT4 IN>; + led = <&PIO17 3 ALT4 OUT>; + }; + }; + }; }; pin-controller-left {