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[209.132.180.67]) by mx.google.com with ESMTP id se1si23586717pbb.225.2014.05.28.07.27.37 for ; Wed, 28 May 2014 07:27:37 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932188AbaE1O13 (ORCPT + 27 others); Wed, 28 May 2014 10:27:29 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:33824 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754425AbaE1O0w (ORCPT ); Wed, 28 May 2014 10:26:52 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s4SEQEhf028723; Wed, 28 May 2014 09:26:14 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4SEQEsW003956; Wed, 28 May 2014 09:26:14 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 28 May 2014 09:26:14 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4SEQDhv010251; Wed, 28 May 2014 09:26:13 -0500 From: Murali Karicheri To: , , CC: Murali Karicheri , Russell King , Bjorn Helgaas , Arnd Bergmann , Jason Gunthorpe Subject: [PATCH] ARM: pci: add call to pcie_bus_configure_settings() Date: Wed, 28 May 2014 10:26:16 -0400 Message-ID: <1401287176-4986-1-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , PCI core supports PCIE_BUS_SAFE and PCIE_BUS_PERFORMANCE modes. PCI controllers may not be able to handle pay load size higher than MPS and also read data size higher than MRSS. So limit the max to the least common supported payload size by calling pcie_bus_configure_settings(). Using pci=pcie_bus_safe do a walk and set the MPS to least common value used by devices on the bus. pci=pcie_bus_perf does do a walk and set MRSS to MPS. This is suggested as a better solution than pci quirk to do similar thing. Signed-off-by: Murali Karicheri CC: Russell King CC: Bjorn Helgaas CC: Arnd Bergmann CC: Jason Gunthorpe --- arch/arm/kernel/bios32.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 16d43cd..537f99e 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -545,6 +545,18 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) */ pci_bus_add_devices(bus); } + + list_for_each_entry(sys, &head, node) { + struct pci_bus *bus = sys->bus; + + /* Configure PCI Express settings */ + if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { + struct pci_bus *child; + + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + } + } } #ifndef CONFIG_PCI_HOST_ITE8152