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[109.148.113.200]) by mx.google.com with ESMTPSA id qo12sm13436327igb.21.2014.05.22.06.53.54 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 06:53:55 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kishon@ti.com Cc: Lee Jones Subject: [PATCH 2/4] phy: miphy365x: Add MiPHY365x header file for DT x Driver defines Date: Thu, 22 May 2014 14:53:37 +0100 Message-Id: <1400766819-22286-3-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400766819-22286-1-git-send-email-lee.jones@linaro.org> References: <1400766819-22286-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.177 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This provides the shared header file which will be reference from both the MiPHY365x driver and its associated Device Tree node(s). Cc: Kishon Vijay Abraham I Acked-by: Mark Rutland Acked-by: Alexandre Torgue Signed-off-by: Lee Jones --- include/dt-bindings/phy/phy-miphy365x.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/phy/phy-miphy365x.h diff --git a/include/dt-bindings/phy/phy-miphy365x.h b/include/dt-bindings/phy/phy-miphy365x.h new file mode 100644 index 0000000..8757c02 --- /dev/null +++ b/include/dt-bindings/phy/phy-miphy365x.h @@ -0,0 +1,25 @@ +/* + * This header provides constants for the phy framework + * based on the STMicroelectronics miphy365x. + */ +#ifndef _DT_BINDINGS_PHY_MIPHY +#define _DT_BINDINGS_PHY_MIPHY + +/* Supports 16 ports without a datatype change (u8 & 0xF0). */ +#define MIPHY_PORT_0 0 +#define MIPHY_PORT_1 1 +#define MIPHY_PORT_2 2 +#define MIPHY_PORT_3 3 + +/* Supports 16 types without a datatype change (u8 & 0x0F). */ +#define MIPHY_TYPE_SHIFT 4 +#define MIPHY_TYPE_SATA (0 << MIPHY_TYPE_SHIFT) +#define MIPHY_TYPE_PCIE (1 << MIPHY_TYPE_SHIFT) +#define MIPHY_TYPE_USB (2 << MIPHY_TYPE_SHIFT) + +#define MIPHY_SATA_PORT0 (MIPHY_TYPE_SATA) | (MIPHY_PORT_0) +#define MIPHY_SATA_PORT1 (MIPHY_TYPE_SATA) | (MIPHY_PORT_1) +#define MIPHY_PCIE_PORT0 (MIPHY_TYPE_PCIE) | (MIPHY_PORT_0) +#define MIPHY_PCIE_PORT1 (MIPHY_TYPE_PCIE) | (MIPHY_PORT_1) + +#endif /* _DT_BINDINGS_PHY_MIPHY */