From patchwork Thu May 22 13:53:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 30625 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qg0-f71.google.com (mail-qg0-f71.google.com [209.85.192.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 14DA520671 for ; Thu, 22 May 2014 13:53:55 +0000 (UTC) Received: by mail-qg0-f71.google.com with SMTP id a108sf7582471qge.10 for ; Thu, 22 May 2014 06:53:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=Xc64ckrsbOnqrtwxc4mlWHPdmA8WNva7TYxoSRj5G1U=; b=hdHc9lzAbGkQhxo2kGSfh9LhL2w4Oi76MK+vAJ6a2bLLLp4kJXo9B5ZG0qfimVssL/ N3KZhtCI2XiVQgoTZknC8n2VLqbGn1Ml6u86R8U7GrpfGI7Erwh3D9kJmv2KdFMcIxGs xhM/jfoZL7Hq260+S+K0Ik9c5VusyRXrwwN0bAkEQOFaPPe4wqIOWUQPQ5HAQcSyBpA6 KF4Tkl9OViEimpq+2vC3gxC96taUuO9JAUREq68+o+2JshBOIgWTwK+QCeLpf0PhbO/K rVCqoHPitREyU4VRGsGbb5NIL0/IdbLr1uec0Xw21l6zhqqyKcuppDZVgMDuqJOQAwui exbQ== X-Gm-Message-State: ALoCoQmObcIt0jJQp8Meh8WZCxkCQh6Gw776LE6IQt/U+osTVfvZ7fP2uyu8b0bIXbNPFR/iWkAW X-Received: by 10.52.2.129 with SMTP id 1mr21776943vdu.4.1400766834935; Thu, 22 May 2014 06:53:54 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.22.103 with SMTP id 94ls466028qgm.4.gmail; Thu, 22 May 2014 06:53:54 -0700 (PDT) X-Received: by 10.220.94.8 with SMTP id x8mr518118vcm.67.1400766834854; Thu, 22 May 2014 06:53:54 -0700 (PDT) Received: from mail-vc0-f181.google.com (mail-vc0-f181.google.com [209.85.220.181]) by mx.google.com with ESMTPS id m3si4876732vcr.51.2014.05.22.06.53.54 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 06:53:54 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) client-ip=209.85.220.181; Received: by mail-vc0-f181.google.com with SMTP id hy4so1074400vcb.40 for ; Thu, 22 May 2014 06:53:54 -0700 (PDT) X-Received: by 10.220.95.2 with SMTP id b2mr533538vcn.61.1400766834747; Thu, 22 May 2014 06:53:54 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp200870vcb; Thu, 22 May 2014 06:53:54 -0700 (PDT) X-Received: by 10.50.2.8 with SMTP id 8mr22315302igq.32.1400766834151; Thu, 22 May 2014 06:53:54 -0700 (PDT) Received: from mail-ig0-f180.google.com (mail-ig0-f180.google.com [209.85.213.180]) by mx.google.com with ESMTPS id lq7si8949248igb.40.2014.05.22.06.53.54 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 06:53:54 -0700 (PDT) Received-SPF: pass (google.com: domain of lee.jones@linaro.org designates 209.85.213.180 as permitted sender) client-ip=209.85.213.180; Received: by mail-ig0-f180.google.com with SMTP id c1so3545685igq.7 for ; Thu, 22 May 2014 06:53:54 -0700 (PDT) X-Received: by 10.42.21.207 with SMTP id l15mr55411498icb.8.1400766833936; Thu, 22 May 2014 06:53:53 -0700 (PDT) Received: from localhost.localdomain (host109-148-113-200.range109-148.btcentralplus.com. [109.148.113.200]) by mx.google.com with ESMTPSA id qo12sm13436327igb.21.2014.05.22.06.53.52 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 06:53:53 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kishon@ti.com Cc: Lee Jones Subject: [PATCH 1/4] phy: miphy365x: Add Device Tree bindings for the MiPHY365x Date: Thu, 22 May 2014 14:53:36 +0100 Message-Id: <1400766819-22286-2-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400766819-22286-1-git-send-email-lee.jones@linaro.org> References: <1400766819-22286-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Cc: Kishon Vijay Abraham I Acked-by: Mark Rutland Acked-by: Alexandre Torgue Signed-off-by: Lee Jones --- .../devicetree/bindings/phy/phy-miphy365x.txt | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy365x.txt diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt new file mode 100644 index 0000000..cb39de1 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt @@ -0,0 +1,62 @@ +STMicroelectronics STi MIPHY365x PHY binding +============================================ + +This binding describes a miphy device that is used to control PHY hardware +for SATA and PCIe. + +Required properties: +- compatible : Should be "st,miphy365x-phy" +- #phy-cells : Should be 2 (See second example) + First cell is the port number from: + - MIPHY_PORT_0 + - MIPHY_PORT_1 + Second cell is device type from: + - MIPHY_TYPE_SATA + - MIPHY_TYPE_PCI +- reg : Address and length of register sets for each device in + "reg-names" +- reg-names : The names of the register addresses corresponding to the + registers filled in "reg", from: + - sata0: For SATA port 0 registers + - sata1: For SATA port 1 registers + - pcie0: For PCIE port 0 registers + - pcie1: For PCIE port 1 registers +- st,syscfg : Should be a phandle of the system configuration register group + which contain the SATA, PCIe mode setting bits + +Optional properties: +- st,sata-gen : Generation of locally attached SATA IP. Expected values + are {1,2,3). If not supplied generation 1 hardware will + be expected +- st,pcie-tx-pol-inv : Bool property to invert the polarity PCIe Tx (Txn/Txp) +- st,sata-tx-pol-inv : Bool property to invert the polarity SATA Tx (Txn/Txp) + +Example: + + miphy365x_phy: miphy365x@fe382000 { + compatible = "st,miphy365x-phy"; + #phy-cells = <2>; + reg = <0xfe382000 0x100>, + <0xfe38a000 0x100>, + <0xfe394000 0x100>, + <0xfe804000 0x100>; + reg-names = "sata0", "sata1", "pcie0", "pcie1"; + st,syscfg = <&syscfg_rear>; + }; + +Specifying phy control of devices +================================= + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the miphy device node, a port number +and a device type. + +Example: + +#include + + sata0: sata@fe380000 { + ... + phys = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>; + ... + };