From patchwork Thu May 22 11:24:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 30601 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ig0-f198.google.com (mail-ig0-f198.google.com [209.85.213.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id AE49720369 for ; Thu, 22 May 2014 11:24:28 +0000 (UTC) Received: by mail-ig0-f198.google.com with SMTP id uq10sf9341115igb.5 for ; Thu, 22 May 2014 04:24:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=19GmQL5cEI8ZXWONV1Wk37cuECwRItvXWczZmIi6Upc=; b=L87ScVWvZtmaJGFysC6JZYx3fLoAyTz6QvRI5ulqMfro2t2YVCZeNogaeGYhluohvU DSwmdBetfP/6kbqgzmEac7N1SJY3wB06+e7TktzFyiBWp/f/OL8eiWtKEfF0mbcjzX/2 FpqSQf+XI9KrYbNGMO9qI0LfURXWzyrbp1tVPG1NldrMzl8UQMG8S9e+bolAD6u/QqxY Cy9YpIeeg4+ZjZUblopCwNvr2vPADjTLQYmGb8GoM03GwELcqIzYqZ6eMpSbqFYqhM0A k1wNlxZs5hApwk68UoNVGIiKt7TwO69/WhtnB4R4CSONFWq3gkaeYGHkChqzQjZaQSL9 Q/5w== X-Gm-Message-State: ALoCoQmCPc7yHVuCbyDo+O3A+anYO/B1QnPUxIXHOp8MMYN9Ict5lUxQ/jTU1lWZHA4hBpbEp8/r X-Received: by 10.42.209.18 with SMTP id ge18mr22307422icb.7.1400757868326; Thu, 22 May 2014 04:24:28 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.36.148 with SMTP id p20ls1178504qgp.80.gmail; Thu, 22 May 2014 04:24:28 -0700 (PDT) X-Received: by 10.58.160.164 with SMTP id xl4mr938635veb.38.1400757868226; Thu, 22 May 2014 04:24:28 -0700 (PDT) Received: from mail-ve0-f174.google.com (mail-ve0-f174.google.com [209.85.128.174]) by mx.google.com with ESMTPS id tv5si4646714vcb.38.2014.05.22.04.24.28 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 04:24:28 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.174 as permitted sender) client-ip=209.85.128.174; Received: by mail-ve0-f174.google.com with SMTP id jw12so4134043veb.5 for ; Thu, 22 May 2014 04:24:28 -0700 (PDT) X-Received: by 10.221.36.73 with SMTP id sz9mr69048vcb.62.1400757868147; Thu, 22 May 2014 04:24:28 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp189958vcb; Thu, 22 May 2014 04:24:27 -0700 (PDT) X-Received: by 10.51.15.161 with SMTP id fp1mr21185426igd.25.1400757866603; Thu, 22 May 2014 04:24:26 -0700 (PDT) Received: from mail-ie0-f171.google.com (mail-ie0-f171.google.com [209.85.223.171]) by mx.google.com with ESMTPS id q6si8244800igr.23.2014.05.22.04.24.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 04:24:26 -0700 (PDT) Received-SPF: pass (google.com: domain of lee.jones@linaro.org designates 209.85.223.171 as permitted sender) client-ip=209.85.223.171; Received: by mail-ie0-f171.google.com with SMTP id to1so3382225ieb.30 for ; Thu, 22 May 2014 04:24:26 -0700 (PDT) X-Received: by 10.50.153.49 with SMTP id vd17mr21483023igb.40.1400757866390; Thu, 22 May 2014 04:24:26 -0700 (PDT) Received: from localhost.localdomain (host109-148-113-200.range109-148.btcentralplus.com. [109.148.113.200]) by mx.google.com with ESMTPSA id z4sm12643314igl.13.2014.05.22.04.24.24 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 22 May 2014 04:24:25 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: computersforpeace@gmail.com, linux-mtd@lists.infradead.org, Angus Clark , Carmelo Amoroso , Lee Jones Subject: [PATCH 04/10] mtd: st_spi_fsm: Add support for N25Q512 and N25Q00A devices Date: Thu, 22 May 2014 12:24:02 +0100 Message-Id: <1400757848-18075-5-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400757848-18075-1-git-send-email-lee.jones@linaro.org> References: <1400757848-18075-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Angus Clark This patch adds support for the Micron N25Q512 and N25Q00A Serial Flash devices. Unlike previous Micron devices, it is now mandatory to check the Flags Status Register following a Write or Erase operation. The N25Q512A device presents a further complication in that different variants of the device use different opcodes for the WRITE_1_4_4 operation. Since there is no easy way to determine at runtime which variant is being used, FLASH_CAPS_WRITE_1_4_4 support is removed for N25Q512 devices, resulting in WRITE_1_1_4 being used instead. The following devices have been tested: b2000C + N25Q512A13GSF40G b2000C + N25Q00AA13GSF40G b2147A + N25Q512A83GSF40X Signed-off-by: Angus Clark Signed-off-by: Carmelo Amoroso Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 96 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 91 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 67ea35e..d48004d 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -225,12 +225,25 @@ #define S25FL_STATUS_E_ERR 0x20 #define S25FL_STATUS_P_ERR 0x40 +/* N25Q - READ/WRITE/CLEAR NON/VOLATILE STATUS/CONFIG Registers */ +#define N25Q_CMD_RFSR 0x70 +#define N25Q_CMD_CLFSR 0x50 #define N25Q_CMD_WRVCR 0x81 #define N25Q_CMD_RDVCR 0x85 #define N25Q_CMD_RDVECR 0x65 #define N25Q_CMD_RDNVCR 0xb5 #define N25Q_CMD_WRNVCR 0xb1 +/* N25Q Flags Status Register: Error Flags */ +#define N25Q_FLAGS_ERR_ERASE BIT(5) +#define N25Q_FLAGS_ERR_PROG BIT(4) +#define N25Q_FLAGS_ERR_VPP BIT(3) +#define N25Q_FLAGS_ERR_PROT BIT(1) +#define N25Q_FLAGS_ERROR (N25Q_FLAGS_ERR_ERASE | \ + N25Q_FLAGS_ERR_PROG | \ + N25Q_FLAGS_ERR_VPP | \ + N25Q_FLAGS_ERR_PROT) + #define FLASH_PAGESIZE 256 /* In Bytes */ #define FLASH_PAGESIZE_32 (FLASH_PAGESIZE / 4) /* In uint32_t */ #define FLASH_MAX_BUSY_WAIT (300 * HZ) /* Maximum 'CHIPERASE' time */ @@ -242,6 +255,7 @@ #define CFG_WRITE_TOGGLE_32BIT_ADDR 0x00000002 #define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008 #define CFG_S25FL_CHECK_ERROR_FLAGS 0x00000010 +#define CFG_N25Q_CHECK_ERROR_FLAGS 0x00000020 struct stfsm_seq { uint32_t data_size; @@ -360,6 +374,7 @@ static struct flash_info flash_types[] = { (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, stfsm_mx25_config}, + /* Micron N25Qxxx */ #define N25Q_FLAG (FLASH_FLAG_READ_WRITE | \ FLASH_FLAG_READ_FAST | \ FLASH_FLAG_READ_1_1_2 | \ @@ -372,10 +387,29 @@ static struct flash_info flash_types[] = { FLASH_FLAG_WRITE_1_4_4) { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, stfsm_n25q_config }, - { "n25q256", 0x20ba19, 0, 64 * 1024, 512, - N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config }, - { "n25q512", 0x20ba20, 0, 64 * 1024, 1024, - N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config}, + + /* Micron N25Q256/N25Q512/N25Q00A (32-bit ADDR devices) + * + * Versions are available with or without a dedicated RESET# pin + * (e.g. N25Q512A83GSF40G vs. N25Q512A13GSF40G). To complicate matters, + * the versions that include a RESET# pin (Feature Set = 8) require a + * different opcode for the FLASH_CMD_WRITE_1_4_4 command. + * Unfortunately it is not possible to determine easily at run-time + * which version is being used. We therefore remove support for + * FLASH_FLAG_WRITE_1_4_4 (falling back to FLASH_FLAG_WRITE_1_1_4), and + * defer overall support for RESET# to the board-level platform/Device + * Tree property "reset-signal". + */ +#define N25Q_32BIT_ADDR_FLAG ((N25Q_FLAG | \ + FLASH_FLAG_32BIT_ADDR | \ + FLASH_FLAG_RESET) & \ + ~FLASH_FLAG_WRITE_1_4_4) + { "n25q256", 0x20ba19, 0, 64 * 1024, 512, + N25Q_32BIT_ADDR_FLAG, 108, stfsm_n25q_config}, + { "n25q512", 0x20ba20, 0x1000, 64 * 1024, 1024, + N25Q_32BIT_ADDR_FLAG, 108, stfsm_n25q_config}, + { "n25q00a", 0x20ba21, 0x1000, 64 * 1024, 2048, + N25Q_32BIT_ADDR_FLAG, 108, stfsm_n25q_config}, /* * Spansion S25FLxxxP @@ -854,6 +888,30 @@ static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf, return size; } +static int n25q_clear_flags(struct stfsm *fsm) +{ + struct stfsm_seq seq = { + .seq_opc[0] = (SEQ_OPC_PADS_1 | + SEQ_OPC_CYCLES(8) | + SEQ_OPC_OPCODE(N25Q_CMD_CLFSR) | + SEQ_OPC_CSDEASSERT), + .seq = { + STFSM_INST_CMD1, + STFSM_INST_STOP, + }, + .seq_cfg = (SEQ_CFG_PADS_1 | + SEQ_CFG_READNOTWRITE | + SEQ_CFG_CSDEASSERT | + SEQ_CFG_STARTSEQ), + }; + + stfsm_load_seq(fsm, &seq); + + stfsm_wait_seq(fsm); + + return 0; +} + static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) { struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; @@ -1214,10 +1272,18 @@ static int stfsm_mx25_config(struct stfsm *fsm) static int stfsm_n25q_config(struct stfsm *fsm) { uint32_t flags = fsm->info->flags; - uint8_t vcr; + uint8_t vcr, sta; int ret = 0; bool soc_reset; + /* + * Check/Clear Error Flags + */ + fsm->configuration |= CFG_N25Q_CHECK_ERROR_FLAGS; + stfsm_read_status(fsm, N25Q_CMD_RFSR, &sta, 1); + if (sta & N25Q_FLAGS_ERROR) + n25q_clear_flags(fsm); + /* Configure 'READ' sequence */ if (flags & FLASH_FLAG_32BIT_ADDR) ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, @@ -1592,6 +1658,7 @@ static int stfsm_write(struct stfsm *fsm, const uint8_t *buf, uint32_t page_buf[FLASH_PAGESIZE_32]; uint8_t *t = (uint8_t *)&tmp; const uint8_t *p; + uint8_t sta; int ret; int i; @@ -1663,6 +1730,15 @@ static int stfsm_write(struct stfsm *fsm, const uint8_t *buf, if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) stfsm_s25fl_clear_status_reg(fsm); + /* N25Q: Check/Clear Error Flags */ + if (fsm->configuration & CFG_N25Q_CHECK_ERROR_FLAGS) { + stfsm_read_status(fsm, N25Q_CMD_RFSR, &sta, 1); + if (sta & N25Q_FLAGS_ERROR) { + n25q_clear_flags(fsm); + ret = -EPROTO; + } + } + /* Exit 32-bit address mode, if required */ if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR) stfsm_enter_32bit_addr(fsm, 0); @@ -1705,6 +1781,7 @@ static int stfsm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, static int stfsm_erase_sector(struct stfsm *fsm, uint32_t offset) { struct stfsm_seq *seq = &stfsm_seq_erase_sector; + uint8_t sta; int ret; dev_dbg(fsm->dev, "erasing sector at 0x%08x\n", offset); @@ -1725,6 +1802,15 @@ static int stfsm_erase_sector(struct stfsm *fsm, uint32_t offset) if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) stfsm_s25fl_clear_status_reg(fsm); + /* N25Q: Check/Clear Error Flags */ + if (fsm->configuration & CFG_N25Q_CHECK_ERROR_FLAGS) { + stfsm_read_status(fsm, N25Q_CMD_RFSR, &sta, 1); + if (sta & N25Q_FLAGS_ERROR) { + n25q_clear_flags(fsm); + ret = -EPROTO; + } + } + /* Exit 32-bit address mode, if required */ if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR) stfsm_enter_32bit_addr(fsm, 0);