From patchwork Tue May 20 14:37:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 30471 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f198.google.com (mail-ie0-f198.google.com [209.85.223.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1728E202FE for ; Tue, 20 May 2014 14:39:49 +0000 (UTC) Received: by mail-ie0-f198.google.com with SMTP id tp5sf2347051ieb.1 for ; Tue, 20 May 2014 07:39:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:content-type:content-transfer-encoding; bh=gA8y1T2ZWrL6lg2lvwOpqd1MVlJ4+RABBdCmmk7XH60=; b=GBDE78+06WKoltlx0dVRm8Z34Z7wMRV/+XpHBnVsvE5TY/XDkYfUahDO3a7vATsQln GpnQEBMUV24Sx3gKIAvx3ZFe3qCdPzYiMUJvuw58a/1ubfRhaZ3FfrQpNQG5EersHSjk BIq/XwD4jhQFJtSnzAGUNqigcXPxnIbR4YZE0YsvcMds0K3JAE+Khro3mw2UHA+1b4P3 zTs1NGTps/iOh54kCGMLySskWPj9qkOUYhMH3P8dKup5uvybQr5AxyLKXk+nTdkUEFdX FbBSMXeP1B5cEskKaR6EBjv3rROZor/Y6o+fCzoIxw2H2g4X56lVttCR4ik3ZWXU5yOJ Xp4Q== X-Gm-Message-State: ALoCoQm+zNYoY6yD9nPBkbA9gx+FKAwyY7IpdKgq8ZwWD7M1T9C7aJWN5FmbrCGSZ2QJIb7X1TLq X-Received: by 10.42.209.18 with SMTP id ge18mr17204434icb.7.1400596789520; Tue, 20 May 2014 07:39:49 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.47.203 with SMTP id m69ls325248qga.84.gmail; Tue, 20 May 2014 07:39:49 -0700 (PDT) X-Received: by 10.58.94.102 with SMTP id db6mr764562veb.79.1400596789338; Tue, 20 May 2014 07:39:49 -0700 (PDT) Received: from mail-vc0-f178.google.com (mail-vc0-f178.google.com [209.85.220.178]) by mx.google.com with ESMTPS id gq7si5019633vdc.194.2014.05.20.07.39.49 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 20 May 2014 07:39:49 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) client-ip=209.85.220.178; Received: by mail-vc0-f178.google.com with SMTP id hq16so730699vcb.9 for ; Tue, 20 May 2014 07:39:49 -0700 (PDT) X-Received: by 10.220.5.129 with SMTP id 1mr869305vcv.71.1400596789251; Tue, 20 May 2014 07:39:49 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp36142vcb; Tue, 20 May 2014 07:39:48 -0700 (PDT) X-Received: by 10.140.20.144 with SMTP id 16mr14494563qgj.114.1400596788611; Tue, 20 May 2014 07:39:48 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id p66si9090105qgp.37.2014.05.20.07.39.48 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 May 2014 07:39:48 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WmlBY-0004W4-OC; Tue, 20 May 2014 14:38:32 +0000 Received: from mail-pb0-f41.google.com ([209.85.160.41]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WmlBV-0004R8-K6 for linux-arm-kernel@lists.infradead.org; Tue, 20 May 2014 14:38:30 +0000 Received: by mail-pb0-f41.google.com with SMTP id uo5so381813pbc.28 for ; Tue, 20 May 2014 07:38:08 -0700 (PDT) X-Received: by 10.68.110.129 with SMTP id ia1mr51471527pbb.158.1400596688539; Tue, 20 May 2014 07:38:08 -0700 (PDT) Received: from localhost.localdomain ([140.206.182.114]) by mx.google.com with ESMTPSA id ga1sm3478917pbb.82.2014.05.20.07.37.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 20 May 2014 07:38:07 -0700 (PDT) From: Haojian Zhuang To: yanhaifeng@gmail.com, xuwei5@hisilicon.com, arnd@arndb.de, olof@lixom.net, linux-arm-kernel@lists.infradead.org, khilman@kernel.org, jchxue@gmail.com Subject: [PATCH v3 4/6] ARM: dts: Add hix5hd2-dkb dts file. Date: Tue, 20 May 2014 22:37:03 +0800 Message-Id: <1400596625-16830-5-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400596625-16830-1-git-send-email-haojian.zhuang@linaro.org> References: <1400596625-16830-1-git-send-email-haojian.zhuang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140520_073829_696687_DA8AB531 X-CRM114-Status: GOOD ( 13.98 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.160.41 listed in list.dnswl.org] Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: haojian.zhuang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Haifeng Yan Add dts file for Hisilicon x5hd2 development kit board. Signed-off-by: Haifeng Yan Signed-off-by: Jiancheng Xue Signed-off-by: Haojian Zhuang --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/hix5hd2-dkb.dts | 52 ++++++++++++ arch/arm/boot/dts/hix5hd2.dtsi | 171 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 224 insertions(+) create mode 100644 arch/arm/boot/dts/hix5hd2-dkb.dts create mode 100644 arch/arm/boot/dts/hix5hd2.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7119bca..54249d9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5440-sd5v1.dtb \ exynos5440-ssdk5440.dtb dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb +dtb-$(CONFIG_ARCH_HIX5HD2) += hix5hd2-dkb.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb diff --git a/arch/arm/boot/dts/hix5hd2-dkb.dts b/arch/arm/boot/dts/hix5hd2-dkb.dts new file mode 100644 index 0000000..d55738b --- /dev/null +++ b/arch/arm/boot/dts/hix5hd2-dkb.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2013-2014 Linaro Ltd. + * Copyright (c) 2013-2014 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/dts-v1/; +#include "hix5hd2.dtsi" + +/ { + model = "Hisilicon HiX5HD2 Development Board"; + compatible = "hisilicon,hix5hd2"; + + chosen { + bootargs = "console=ttyAMA0,115200 earlyprintk"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; + }; +}; + +&timer0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/hix5hd2.dtsi b/arch/arm/boot/dts/hix5hd2.dtsi new file mode 100644 index 0000000..73f9ac1 --- /dev/null +++ b/arch/arm/boot/dts/hix5hd2.dtsi @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2013-2014 Linaro Ltd. + * Copyright (c) 2013-2014 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include + +/ { + aliases { + serial0 = &uart0; + }; + + gic: interrupt-controller@f8a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + /* gic dist base, gic cpu base */ + reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0 0xf8000000 0x8000000>; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + ranges; + + timer0: timer@00002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00002000 0x1000>; + /* timer00 & timer01 */ + interrupts = <0 24 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer1: timer@00a29000 { + /* + * Only used in NORMAL state, not available ins + * SLOW or DOZE state. + * The rate is fixed in 24MHz. + */ + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a29000 0x1000>; + /* timer10 & timer11 */ + interrupts = <0 25 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer2: timer@00a2a000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a2a000 0x1000>; + /* timer20 & timer21 */ + interrupts = <0 26 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer3: timer@00a2b000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a2b000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 27 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + timer4: timer@00a81000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00a81000 0x1000>; + /* timer30 & timer31 */ + interrupts = <0 28 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + status = "disabled"; + }; + + uart0: uart@00b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00b00000 0x1000>; + interrupts = <0 49 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart1: uart@00006000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00006000 0x1000>; + interrupts = <0 50 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart2: uart@00b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00b02000 0x1000>; + interrupts = <0 51 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart3: uart@00b03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00b03000 0x1000>; + interrupts = <0 52 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart4: uart@00b04000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb04000 0x1000>; + interrupts = <0 53 4>; + clocks = <&clock HIX5HD2_FIXED_83M>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + }; + + local_timer@00a00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x00a00600 0x20>; + interrupts = <1 13 0xf01>; + }; + + l2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x00a10000 0x100000>; + interrupts = <0 15 4>; + cache-unified; + cache-level = <2>; + hisilicon,l2cache-aux = <0x00050000 0xfff0ffff>; + }; + + sysctrl: system-controller@00000000 { + compatible = "hisilicon,sysctrl"; + reg = <0x00000000 0x1000>; + reboot-offset = <0x4>; + }; + + cpuctrl@00a22000 { + compatible = "hisilicon,cpuctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00a22000 0x2000>; + ranges = <0 0x00a22000 0x2000>; + + clock: clock@0 { + compatible = "hisilicon,hix5hd2-clock"; + reg = <0 0x2000>; + #clock-cells = <1>; + }; + }; + }; +};