From patchwork Mon May 5 16:26:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 29661 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qg0-f71.google.com (mail-qg0-f71.google.com [209.85.192.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D57DB2055D for ; Mon, 5 May 2014 16:27:28 +0000 (UTC) Received: by mail-qg0-f71.google.com with SMTP id a108sf3158133qge.6 for ; Mon, 05 May 2014 09:27:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=mHrx1mTSNJ7ZNWP9Z++CgHAfdmAMFQcbnE8ms/sKbns=; b=VQHEnPnkTaVJyqWMLr/FHR07bkAHo8YxtO9Pckv4ahSuST0EMR0bjSC4XXCE6g0EML vij6vKARskGmb/SvVhZCUNw3gM1VfPGgNeUCu/dYY+W8k0IqjU9n3ZE/jAfyvJcZDeQv oKI3HyyU5PlYzek7HfqdEGgNQCcCbbrKHs3ObRNuZU/kPZHkV74fPxjd7QYbSWyREVd1 UenupWMG4NCZBFFRgLF3Dc+2MPxVUEOtXjwAt4Mn7RqORyybbwjnMVxLjx919fZOjiRX +b50b4rgp8JOcXfzXrKAUnn1hXn3PqyoVFWN4cTC3vV3HauOT7B98NVQ6AMETBryikkG vaBA== X-Gm-Message-State: ALoCoQl3Ma/KQK+GJ6jlV2Wo/T7VBBPn+qpH5bbXibzfmja/0NfidqzXe8/OseioHB7y8AXY/44D X-Received: by 10.58.178.81 with SMTP id cw17mr16527307vec.37.1399307248536; Mon, 05 May 2014 09:27:28 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.94.118 with SMTP id f109ls2357385qge.8.gmail; Mon, 05 May 2014 09:27:28 -0700 (PDT) X-Received: by 10.52.166.18 with SMTP id zc18mr782084vdb.65.1399307248391; Mon, 05 May 2014 09:27:28 -0700 (PDT) Received: from mail-ve0-x234.google.com (mail-ve0-x234.google.com [2607:f8b0:400c:c01::234]) by mx.google.com with ESMTPS id ls10si1702540vec.172.2014.05.05.09.27.28 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 05 May 2014 09:27:28 -0700 (PDT) Received-SPF: none (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) client-ip=2607:f8b0:400c:c01::234; Received: by mail-ve0-f180.google.com with SMTP id db12so5584628veb.11 for ; Mon, 05 May 2014 09:27:28 -0700 (PDT) X-Received: by 10.58.181.170 with SMTP id dx10mr3368359vec.25.1399307248312; Mon, 05 May 2014 09:27:28 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp153712vcb; Mon, 5 May 2014 09:27:27 -0700 (PDT) X-Received: by 10.66.184.239 with SMTP id ex15mr25707750pac.122.1399307246954; Mon, 05 May 2014 09:27:26 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id to1si9031711pab.486.2014.05.05.09.27.26; Mon, 05 May 2014 09:27:26 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753629AbaEEQ1Z (ORCPT + 9 others); Mon, 5 May 2014 12:27:25 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:39786 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753587AbaEEQ1Z (ORCPT ); Mon, 5 May 2014 12:27:25 -0400 Received: by mail-pa0-f50.google.com with SMTP id fb1so2816456pad.23 for ; Mon, 05 May 2014 09:27:24 -0700 (PDT) X-Received: by 10.66.66.108 with SMTP id e12mr74526928pat.35.1399307244550; Mon, 05 May 2014 09:27:24 -0700 (PDT) Received: from localhost.localdomain ([122.171.76.161]) by mx.google.com with ESMTPSA id f5sm74977298pat.11.2014.05.05.09.27.16 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 05 May 2014 09:27:23 -0700 (PDT) From: Abhilash Kesavan To: nicolas.pitre@linaro.org, Dave.Martin@arm.com, lorenzo.pieralisi@arm.com, daniel.lezcano@linaro.org, linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, t.figa@samsung.com, abrestic@chromium.org, thomas.ab@samsung.com, inderpal.s@samsung.com Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, grant.likely@linaro.org, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, kesavan.abhilash@gmail.com, linux-samsung-soc@vger.kernel.org Subject: [PATCH v5 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs Date: Mon, 5 May 2014 21:56:57 +0530 Message-Id: <1399307221-8659-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399307221-8659-1-git-send-email-a.kesavan@samsung.com> References: <1399307221-8659-1-git-send-email-a.kesavan@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Original-Sender: a.kesavan@samsung.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=neutral (body hash did not verify) header.i=@ Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Leela Krishna Amudala Add generic cpu power control functions for exynos based SoCS for cpu power up/down and to know the cpu status. Signed-off-by: Leela Krishna Amudala --- arch/arm/mach-exynos/common.h | 3 +++ arch/arm/mach-exynos/pm.c | 36 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 3 files changed, 45 insertions(+) diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 47cbab0..a7dbb5f 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -63,5 +63,8 @@ struct exynos_pmu_conf { }; extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); +extern void exynos_cpu_powerdown(int cpu); +extern void exynos_cpu_powerup(int cpu); +extern int exynos_cpu_power_state(int cpu); #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 15af0ce..6651028 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -100,6 +100,42 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) return -ENOENT; } +/** + * exynos_cpu_powerdown : power down the specified cpu + * @cpu : the cpu to power down + * + * Power downs the specified cpu. The sequence must be finished by a + * call to cpu_do_idle() + * + */ +void exynos_cpu_powerdown(int cpu) +{ + __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); +} + +/** + * exynos_cpu_powerup : power up the specified cpu + * @cpu : the cpu to power up + * + * Power up the specified cpu + */ +void exynos_cpu_powerup(int cpu) +{ + __raw_writel(S5P_CORE_LOCAL_PWR_EN, + EXYNOS_ARM_CORE_CONFIGURATION(cpu)); +} + +/** + * exynos_cpu_power_state : returns the power state of the cpu + * @cpu : the cpu to retrieve the power state from + * + */ +int exynos_cpu_power_state(int cpu) +{ + return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & + S5P_CORE_LOCAL_PWR_EN); +} + /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 4f6a256..0bdfcbc 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -121,6 +121,12 @@ #define S5P_CHECK_SLEEP 0x00000BAD +#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ + (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) +#define EXYNOS_ARM_CORE_STATUS(_nr) \ + (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) + /* Only for EXYNOS4210 */ #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)