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[83.153.85.71]) by mx.google.com with ESMTPSA id kp5sm41727776wjb.30.2014.05.01.08.51.35 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 01 May 2014 08:51:35 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, steve.capper@linaro.org, Ard Biesheuvel Subject: [PATCH resend 12/15] arm64/crypto: add shared macro to test for NEED_RESCHED Date: Thu, 1 May 2014 17:51:23 +0200 Message-Id: <1398959486-8222-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1398959486-8222-1-git-send-email-ard.biesheuvel@linaro.org> References: <1398959486-8222-1-git-send-email-ard.biesheuvel@linaro.org> Sender: linux-crypto-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This adds the asm macro definition 'b_if_no_resched' that performs a conditional branch depending on the preempt need_resched state. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/assembler.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index fd3e3924041b..296105fd3021 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -22,6 +22,11 @@ #include +#if defined(CONFIG_PREEMPT) || defined(CONFIG_PREEMPT_VOLUNTARY) +#include +#include +#endif + /* * Stack pushing/popping (register pairs only). Equivalent to store decrement * before, load increment after. @@ -146,3 +151,19 @@ lr .req x30 // link register #endif orr \rd, \lbits, \hbits, lsl #32 .endm + +/* + * Branch to 'lb' but only if we have not been tagged for preemption. + * + * Expects current->thread_info in ti, or NULL if running in interrupt + * context. reg is a scratch x register. + */ + .macro b_if_no_resched, ti, reg, lb +#if defined(CONFIG_PREEMPT) || defined(CONFIG_PREEMPT_VOLUNTARY) + cbz \ti, \lb /* have thread_info? */ + ldr \reg, [\ti, #TI_FLAGS] /* get flags */ + tbz \reg, #TIF_NEED_RESCHED, \lb /* need rescheduling? */ +#else + b \lb +#endif + .endm