From patchwork Tue Apr 29 23:36:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zi Shen Lim X-Patchwork-Id: 29380 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qc0-f197.google.com (mail-qc0-f197.google.com [209.85.216.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 6DA1A202DD for ; Tue, 29 Apr 2014 23:36:38 +0000 (UTC) Received: by mail-qc0-f197.google.com with SMTP id i8sf3021048qcq.0 for ; Tue, 29 Apr 2014 16:36:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :mime-version:sender:precedence:list-id:x-original-sender :x-original-authentication-results:mailing-list:list-post:list-help :list-archive:list-unsubscribe:content-type; bh=+MVBqgri/6vn16x3hz+r1fASn8OkxIojSEcuVOwbVOI=; b=ZJ8d9OQQtwqTYyWPP5MvqeFkgQ+QunGC57+EDSlZGJT1IlGcHFXoRp2vYuW+evLXrO aBBWlIVGCPpz+yBCRz5BbHTVJnj3UHdHQqYZwqrk1ianzMxgTPCBPUxVuYIBHPHi6Xj6 y8qA1/htK35pV/JUqjoQGdMGuXPlLJovaXL2GMbA1sT2OAKnMefreShnJ9dsaSsucdG4 vyVrCOh1iSskUB8cn0uVZM2dSjHAgzB2vTakFWKY7uc1NH9E756C4rY+cgP0YWA/SdgJ xBwl7cTECr8QbqEc3ffSS57lK4x68wovsi3Nx7OIGkxDh6fB2EN/g3OVcAc9G0XXEYgh 7Aeg== X-Gm-Message-State: ALoCoQk84Fl67w6DI2StXcKT5E51gVqSRNN+7JbtKdMRuyCapD27h4M3qJRZLN3y7TjUTOvN7Oiw X-Received: by 10.58.18.200 with SMTP id y8mr485558ved.20.1398814597938; Tue, 29 Apr 2014 16:36:37 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.91.201 with SMTP id z67ls350202qgd.59.gmail; Tue, 29 Apr 2014 16:36:37 -0700 (PDT) X-Received: by 10.58.1.5 with SMTP id 5mr714131vei.8.1398814597849; Tue, 29 Apr 2014 16:36:37 -0700 (PDT) Received: from mail-vc0-f177.google.com (mail-vc0-f177.google.com [209.85.220.177]) by mx.google.com with ESMTPS id fn10si4907755vdc.207.2014.04.29.16.36.37 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 29 Apr 2014 16:36:37 -0700 (PDT) Received-SPF: none (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) client-ip=209.85.220.177; Received: by mail-vc0-f177.google.com with SMTP id if11so1239873vcb.36 for ; Tue, 29 Apr 2014 16:36:37 -0700 (PDT) X-Received: by 10.52.173.165 with SMTP id bl5mr487196vdc.13.1398814597734; Tue, 29 Apr 2014 16:36:37 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp235389vcb; Tue, 29 Apr 2014 16:36:37 -0700 (PDT) X-Received: by 10.67.4.138 with SMTP id ce10mr1875533pad.12.1398814596645; Tue, 29 Apr 2014 16:36:36 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id qf5si14602500pac.416.2014.04.29.16.36.35; Tue, 29 Apr 2014 16:36:35 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754101AbaD2XgZ (ORCPT + 28 others); Tue, 29 Apr 2014 19:36:25 -0400 Received: from mail-gw1-out.broadcom.com ([216.31.210.62]:56920 "EHLO mail-gw1-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751668AbaD2XgW (ORCPT ); Tue, 29 Apr 2014 19:36:22 -0400 X-IronPort-AV: E=Sophos;i="4.97,954,1389772800"; d="scan'208";a="27289553" Received: from irvexchcas06.broadcom.com (HELO IRVEXCHCAS06.corp.ad.broadcom.com) ([10.9.208.53]) by mail-gw1-out.broadcom.com with ESMTP; 29 Apr 2014 17:47:00 -0700 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 29 Apr 2014 16:36:20 -0700 Received: from mail-sj1-12.sj.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.3.174.1; Tue, 29 Apr 2014 16:36:21 -0700 Received: from lc-sj1-5012.broadcom.com (lc-sj1-5012.sj.broadcom.com [10.66.65.230]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 5C48127A81; Tue, 29 Apr 2014 16:36:21 -0700 (PDT) Received: by lc-sj1-5012.broadcom.com (Postfix, from userid 28931) id 50F71E01E79; Tue, 29 Apr 2014 16:36:21 -0700 (PDT) From: Zi Shen Lim To: Lorenzo Pieralisi , Mark Brown , Catalin Marinas , Mark Rutland , Will Deacon CC: Zi Shen Lim , , Subject: [PATCHv3] arm64: topology: add MPIDR-based detection Date: Tue, 29 Apr 2014 16:36:13 -0700 Message-ID: <1398814573-27389-1-git-send-email-zlim@broadcom.com> X-Mailer: git-send-email 1.8.4.3 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: zlim@broadcom.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Create cpu topology based on MPIDR. When hardware sets MPIDR to sane values, this method will always work. Therefore it should also work well as the fallback method. [1] When we have multiple processing elements in the system, we create the cpu topology by mapping each affinity level (from lowest to highest) to threads (if they exist), cores, and clusters. We combine data from all higher affinity levels into cluster_id so we don't lose any information from MPIDR. [2] [1] http://www.spinics.net/lists/arm-kernel/msg317445.html [2] https://lkml.org/lkml/2014/4/23/703 Signed-off-by: Zi Shen Lim --- v1->v2: Addressed comments from Mark Brown. - Reduce noise. Use pr_debug instead of pr_info. - Don't ignore higher affinity levels. v2->v3: Addressed comments from Lorenzo Pieralisi. - Rebased on top of Mark Brown's DT topology series. - Make MPIDR fallback option. - Fixed usage of mpidr_hash.shift_aff. Please review :) Tested on my multi-core multi-thread model. arch/arm64/include/asm/cputype.h | 5 +++++ arch/arm64/kernel/topology.c | 44 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index c404fb0..b3b3287 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -18,6 +18,8 @@ #define INVALID_HWID ULONG_MAX +#define MPIDR_UP_BITMASK (0x1 << 30) +#define MPIDR_MT_BITMASK (0x1 << 24) #define MPIDR_HWID_BITMASK 0xff00ffffff #define MPIDR_LEVEL_BITS_SHIFT 3 @@ -30,6 +32,9 @@ #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) +#define MPIDR_AFF_MASK(level) \ + ((u64)MPIDR_LEVEL_MASK << MPIDR_LEVEL_SHIFT(level)) + #define read_cpuid(reg) ({ \ u64 __val; \ asm("mrs %0, " #reg : "=r" (__val)); \ diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index caf2a7c..cfaa2a3 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -21,6 +21,8 @@ #include #include +#include +#include #include /* @@ -362,9 +364,7 @@ static void update_siblings_masks(unsigned int cpuid) int cpu; if (cpuid_topo->cluster_id == -1) { - /* - * DT does not contain topology information for this cpu. - */ + /* No topology information for this cpu ?! */ pr_debug("CPU%u: No topology information configured\n", cpuid); return; } @@ -391,6 +391,44 @@ static void update_siblings_masks(unsigned int cpuid) void store_cpu_topology(unsigned int cpuid) { + struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; + u64 mpidr; + + if (cpuid_topo->cluster_id != -1) + goto topology_populated; + + mpidr = read_cpuid_mpidr(); + + /* Create cpu topology mapping based on MPIDR. */ + if (mpidr & MPIDR_UP_BITMASK) { + /* Uniprocessor system */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cpuid_topo->cluster_id = 0; + } else if (mpidr & MPIDR_MT_BITMASK) { + /* Multiprocessor system : Multi-threads per core */ + cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); + cpuid_topo->cluster_id = + ((mpidr & MPIDR_AFF_MASK(2)) >> mpidr_hash.shift_aff[2] | + (mpidr & MPIDR_AFF_MASK(3)) >> mpidr_hash.shift_aff[3]) + >> mpidr_hash.shift_aff[1] >> mpidr_hash.shift_aff[0]; + } else { + /* Multiprocessor system : Single-thread per core */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cpuid_topo->cluster_id = + ((mpidr & MPIDR_AFF_MASK(1)) >> mpidr_hash.shift_aff[1] | + (mpidr & MPIDR_AFF_MASK(2)) >> mpidr_hash.shift_aff[2] | + (mpidr & MPIDR_AFF_MASK(3)) >> mpidr_hash.shift_aff[3]) + >> mpidr_hash.shift_aff[0]; + } + + pr_debug("CPU%u: cluster %d core %d thread %d mpidr %llx\n", + cpuid, cpuid_topo->cluster_id, cpuid_topo->core_id, + cpuid_topo->thread_id, mpidr); + +topology_populated: update_siblings_masks(cpuid); update_cpu_power(cpuid); }