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[209.132.180.67]) by mx.google.com with ESMTP id ci3si4829435pad.455.2014.04.25.06.23.52; Fri, 25 Apr 2014 06:23:52 -0700 (PDT) Received-SPF: none (google.com: linux-acpi-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753863AbaDYNXq (ORCPT + 8 others); Fri, 25 Apr 2014 09:23:46 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:39965 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753871AbaDYNXn (ORCPT ); Fri, 25 Apr 2014 09:23:43 -0400 Received: by mail-pa0-f49.google.com with SMTP id lj1so3109682pab.8 for ; Fri, 25 Apr 2014 06:23:43 -0700 (PDT) X-Received: by 10.66.240.70 with SMTP id vy6mr7837868pac.80.1398432223075; Fri, 25 Apr 2014 06:23:43 -0700 (PDT) Received: from localhost ([218.17.215.175]) by mx.google.com with ESMTPSA id pr4sm15959360pbb.53.2014.04.25.06.23.33 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 25 Apr 2014 06:23:42 -0700 (PDT) From: Hanjun Guo To: linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: "Rafael J. Wysocki" , Catalin Marinas , Arnd Bergmann , Mark Brown , Grant Likely , Sudeep Holla , Olof Johansson , Mark Rutland , Rob Herring , Will Deacon , Charles.Garcia-Tobin@arm.com, linaro-acpi@lists.linaro.org, Hanjun Guo , Graeme Gregory , Al Stone Subject: [PATCH v3 part1 08/11] ARM64 / ACPI: Introduce PCI functions for ACPI on ARM64 Date: Fri, 25 Apr 2014 21:20:14 +0800 Message-Id: <1398432017-8506-9-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398432017-8506-1-git-send-email-hanjun.guo@linaro.org> References: <1398432017-8506-1-git-send-email-hanjun.guo@linaro.org> Sender: linux-acpi-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: hanjun.guo@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , CONFIG_ACPI depends CONFIG_PCI now, and ACPI provides ACPI based PCI hotplug and PCI host bridge hotplug, introduce some PCI functions to make ACPI core can be compiled, some of the functions should be revisited when implemented on ARM64. Signed-off-by: Hanjun Guo Signed-off-by: Graeme Gregory Signed-off-by: Al Stone --- arch/arm64/include/asm/pci.h | 11 +++++++++++ arch/arm64/kernel/pci.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h index d93576f..0aa3607 100644 --- a/arch/arm64/include/asm/pci.h +++ b/arch/arm64/include/asm/pci.h @@ -21,6 +21,17 @@ struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus); #define pcibios_assign_all_busses() \ (pci_has_flag(PCI_REASSIGN_ALL_BUS)) +static inline void pcibios_penalize_isa_irq(int irq, int active) +{ + /* we don't do dynamic pci irq allocation */ +} + +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) +{ + /* no legacy IRQ on arm64 */ + return -ENODEV; +} + /* * PCI address space differs from physical memory address space */ diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index 9f29c9a..df90bad 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -17,6 +17,7 @@ #include #include #include +#include #include @@ -171,3 +172,36 @@ unsigned long pci_ioremap_io(const struct resource *res, phys_addr_t phys_addr) /* return io_offset */ return start * PAGE_SIZE - res->start; } + +/* + * raw_pci_read - Platform-specific PCI config space access. + * + * Default empty implementation. Replace with an architecture-specific setup + * routine, if necessary. + */ +int raw_pci_read(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *val) +{ + return -EINVAL; +} + +int raw_pci_write(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 val) +{ + return -EINVAL; +} + +#ifdef CONFIG_ACPI +/* Root bridge scanning */ +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + /* TODO: Should be revisited when implementing PCI on ACPI */ + return NULL; +} + +void __init pci_acpi_crs_quirks(void) +{ + /* Do nothing on ARM64 */ + return; +} +#endif