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[2001:770:15f::2]) by mx.google.com with ESMTPS id fy14si1035677wjc.5.2014.04.08.08.29.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Apr 2014 08:29:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WXXwP-0007Tb-W5; Tue, 08 Apr 2014 15:28:02 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WXXwJ-0005am-Qv; Tue, 08 Apr 2014 15:27:55 +0000 Received: from bombadil.infradead.org ([2001:1868:205::9]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WXXjv-0003gg-73 for linux-arm-kernel@merlin.infradead.org; Tue, 08 Apr 2014 15:15:07 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WXQzF-0000ut-0F for linux-arm-kernel@lists.infradead.org; Tue, 08 Apr 2014 08:02:29 +0000 Received: by mail-pa0-f49.google.com with SMTP id lj1so685969pab.36 for ; Tue, 08 Apr 2014 01:02:06 -0700 (PDT) X-Received: by 10.66.189.201 with SMTP id gk9mr2726529pac.25.1396944126827; Tue, 08 Apr 2014 01:02:06 -0700 (PDT) Received: from localhost.localdomain ([162.243.130.63]) by mx.google.com with ESMTPSA id it4sm2764630pbd.48.2014.04.08.01.02.01 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Apr 2014 01:02:05 -0700 (PDT) From: Haojian Zhuang To: linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, linux@arm.linux.org.uk, arnd@arndb.de, olof@lixom.net, khilman@kernel.org, xuwei5@hisilicon.com Subject: [PATCH v2 12/12] ARM: dts: Add PMU support in HiP04 Date: Tue, 8 Apr 2014 16:00:52 +0800 Message-Id: <1396944052-9887-13-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396944052-9887-1-git-send-email-haojian.zhuang@linaro.org> References: <1396944052-9887-1-git-send-email-haojian.zhuang@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140408_010229_066205_CEA3617F X-CRM114-Status: UNSURE ( 9.76 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.49 listed in list.dnswl.org] Cc: Haojian Zhuang , Kefeng Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: haojian.zhuang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Kefeng Wang ARM Performance Monitor Units are available on the HiP04. So add the support in the dtsi. Simply tested with perf. Signed-off-by: Kefeng Wang Signed-off-by: Haojian Zhuang --- arch/arm/boot/dts/hip04.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index eb5e5a2..0ad1e7b 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -219,6 +219,26 @@ status = "ok"; }; + arm-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 64 4>, + <0 65 4>, + <0 66 4>, + <0 67 4>, + <0 68 4>, + <0 69 4>, + <0 70 4>, + <0 71 4>, + <0 72 4>, + <0 73 4>, + <0 74 4>, + <0 75 4>, + <0 76 4>, + <0 77 4>, + <0 78 4>, + <0 79 4>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <1 13 0xf08>,