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[128.107.239.233]) by mx.google.com with ESMTPSA id ei4sm1097725pbb.42.2014.04.07.20.04.39 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 07 Apr 2014 20:04:40 -0700 (PDT) From: Victor Kamensky To: linux-arm-kernel@lists.infradead.org, dave.long@linaro.org, oleg@redhat.com Subject: [RFC PATCH] ARM: uprobes need icache flush after xol write Date: Mon, 7 Apr 2014 20:04:20 -0700 Message-Id: <1396926260-7705-2-git-send-email-victor.kamensky@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1396926260-7705-1-git-send-email-victor.kamensky@linaro.org> References: <1396926260-7705-1-git-send-email-victor.kamensky@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140407_200509_356480_7F4721AA X-CRM114-Status: GOOD ( 14.20 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.192.171 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record Cc: tixy@linaro.org, linaro-kernel@lists.linaro.org, ananth@in.ibm.com, Victor Kamensky , taras.kondratiuk@linaro.org, will.deacon@arm.com, rabin@rab.in, Dave.Martin@arm.com, rmk@arm.linux.org.uk X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: victor.kamensky@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 After instruction write into xol area, on ARM V7 architecture code need to flush icache to sync up dcache and icache. Having just 'flush_dcache_page(page)' call is not enough - it is possible to have stale instruction sitting in icache for given xol area slot address. Introduce arch_uprobe_xol_sync_dcache_icache weak function that by default calls 'flush_dcache_page(page)' and on ARM define one that calls __cpuc_coherent_user_range. Signed-off-by: Victor Kamensky --- arch/arm/kernel/uprobes.c | 6 ++++++ include/linux/uprobes.h | 3 +++ kernel/events/uprobes.c | 20 +++++++++++++++----- 3 files changed, 24 insertions(+), 5 deletions(-) diff --git a/arch/arm/kernel/uprobes.c b/arch/arm/kernel/uprobes.c index f9bacee..841750b 100644 --- a/arch/arm/kernel/uprobes.c +++ b/arch/arm/kernel/uprobes.c @@ -113,6 +113,12 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, return 0; } +void arch_uprobe_xol_sync_dcache_icache(struct page *page, + unsigned long addr, unsigned long size) +{ + __cpuc_coherent_user_range(addr, size); +} + int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) { struct uprobe_task *utask = current->utask; diff --git a/include/linux/uprobes.h b/include/linux/uprobes.h index edff2b9..2fe3dfd 100644 --- a/include/linux/uprobes.h +++ b/include/linux/uprobes.h @@ -32,6 +32,7 @@ struct vm_area_struct; struct mm_struct; struct inode; struct notifier_block; +struct page; #define UPROBE_HANDLER_REMOVE 1 #define UPROBE_HANDLER_MASK 1 @@ -127,6 +128,8 @@ extern int arch_uprobe_exception_notify(struct notifier_block *self, unsigned l extern void arch_uprobe_abort_xol(struct arch_uprobe *aup, struct pt_regs *regs); extern unsigned long arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs); extern bool __weak arch_uprobe_ignore(struct arch_uprobe *aup, struct pt_regs *regs); +extern void __weak arch_uprobe_xol_sync_dcache_icache(struct page *page, + unsigned long addr, unsigned long size); #else /* !CONFIG_UPROBES */ struct uprobes_state { }; diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c index 04709b6..0027883 100644 --- a/kernel/events/uprobes.c +++ b/kernel/events/uprobes.c @@ -1299,11 +1299,9 @@ static unsigned long xol_get_insn_slot(struct uprobe *uprobe) /* Initialize the slot */ copy_to_page(area->page, xol_vaddr, &uprobe->arch.ixol, sizeof(uprobe->arch.ixol)); - /* - * We probably need flush_icache_user_range() but it needs vma. - * This should work on supported architectures too. - */ - flush_dcache_page(area->page); + + arch_uprobe_xol_sync_dcache_icache(area->page, + xol_vaddr, sizeof(uprobe->arch.ixol)); return xol_vaddr; } @@ -1346,6 +1344,18 @@ static void xol_free_insn_slot(struct task_struct *tsk) } } +void __weak arch_uprobe_xol_sync_dcache_icache(struct page *page, + unsigned long addr, unsigned long len) +{ + /* + * We probably need flush_icache_user_range() but it needs vma. + * This should work on most of architectures by default. If + * architecture needs to do something different it can define + * its own version of the function. + */ + flush_dcache_page(page); +} + /** * uprobe_get_swbp_addr - compute address of swbp given post-swbp regs * @regs: Reflects the saved state of the task after it has hit a breakpoint