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Mon, 24 Mar 2014 02:10:05 -0700 (PDT) From: mohun106@gmail.com To: Catalin.Marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, pkapoor@caviumnetworks.com, Radha Mohan Chintakuntla Subject: [PATCH v2 2/3] arm64: dts: Add initial dts for Cavium Thunder SoC Date: Mon, 24 Mar 2014 14:39:38 +0530 Message-Id: <1395652179-9216-3-git-send-email-mohun106@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1395652179-9216-1-git-send-email-mohun106@gmail.com> References: <1395652179-9216-1-git-send-email-mohun106@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Original-Sender: mohun106@gmail.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::234 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=neutral (no key for signature) header.i=@gmail.com; dmarc=fail (p=NONE dis=NONE) header.from=gmail.com Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Radha Mohan Chintakuntla Signed-off-by: Radha Mohan Chintakuntla --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/thunder.dts | 160 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 161 insertions(+), 0 deletions(-) diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index c52bdb0..9cc8740 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_THUNDER) += thunder.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb diff --git a/arch/arm64/boot/dts/thunder.dts b/arch/arm64/boot/dts/thunder.dts new file mode 100644 index 0000000..190e01a --- /dev/null +++ b/arch/arm64/boot/dts/thunder.dts @@ -0,0 +1,160 @@ +/* + * Cavium Thunder DTS file + * + * Copyright (C) 2013, Cavium Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { + model = "Cavium Thunder"; + compatible = "cavium,thunder"; + interrupt-parent = <&gic0>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uaa0; + serial1 = &uaa1; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + }; + cpu@4 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x4>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + }; + cpu@5 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x5>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + }; + cpu@6 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x6>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + }; + cpu@7 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x7>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + }; + + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gic0: interrupt-controller@801000000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x8010 0x0 0x0 0x10000>, /* GICD */ + <0x8010 0x80000000 0x0 0x100000>; /* GICR */ + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + }; + + ahci0: host-bus-adapter@810000000000 { + compatible = "snps,spear-ahci"; + reg = <0x8100 0x0 0x0 0x1100>; + interrupts = <1 32 4>; + }; + + nic0: ethernet@843000000000 { + compatible = "smsc,lan9115"; + reg-io-width = <4>; + reg = <0x8430 0x0 0x0 0x1000>; + interrupts = <1 31 4>; + }; + + uaa0: uart@87e024000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x24000000 0x0 0x1000>; + interrupts = <1 21 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + }; + + uaa1: uart@87e025000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x25000000 0x0 0x1000>; + interrupts = <1 22 4>; + clocks = <&refclk50mhz>; + clock-names = "apb_pclk"; + }; + }; +};