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[209.132.180.67]) by mx.google.com with ESMTP id zo6si762588pbc.313.2014.03.12.20.33.14; Wed, 12 Mar 2014 20:33:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753079AbaCMDdN (ORCPT + 8 others); Wed, 12 Mar 2014 23:33:13 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:37574 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752966AbaCMDdN (ORCPT ); Wed, 12 Mar 2014 23:33:13 -0400 Received: by mail-pd0-f170.google.com with SMTP id v10so458684pde.29 for ; Wed, 12 Mar 2014 20:33:12 -0700 (PDT) X-Received: by 10.68.216.133 with SMTP id oq5mr1477353pbc.72.1394681592753; Wed, 12 Mar 2014 20:33:12 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id zl2sm2498814pac.7.2014.03.12.20.33.10 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 12 Mar 2014 20:33:12 -0700 (PDT) From: Sachin Kamat To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, t.figa@samsung.com, mturquette@linaro.org, sachin.kamat@linaro.org Subject: [PATCH 1/1] clk: exynos-5420: Fix VPLL lock offset Date: Thu, 13 Mar 2014 08:57:02 +0530 Message-Id: <1394681222-27882-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. 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Signed-off-by: Sachin Kamat --- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 60b26819bed5..7fd6bea467fd 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -33,7 +33,7 @@ #define RPLL_LOCK 0x10050 #define IPLL_LOCK 0x10060 #define SPLL_LOCK 0x10070 -#define VPLL_LOCK 0x10070 +#define VPLL_LOCK 0x10080 #define MPLL_LOCK 0x10090 #define CPLL_CON0 0x10120 #define DPLL_CON0 0x10128