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[109.148.116.196]) by mx.google.com with ESMTPSA id dk9sm69664476wjb.4.2014.03.12.06.15.33 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 12 Mar 2014 06:15:34 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: lee.jones@linaro.org, kernel@stlinux.com, alexandre.torgue@st.com, Srinivas Kandagatla Subject: [PATCH 3/4] ARM: DT: STi: Add DT node for MiPHY365x Date: Wed, 12 Mar 2014 13:14:55 +0000 Message-Id: <1394630096-28564-4-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1394630096-28564-1-git-send-email-lee.jones@linaro.org> References: <1394630096-28564-1-git-send-email-lee.jones@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Cc: Srinivas Kandagatla Acked-by: Mark Rutland Acked-by: Alexandre Torgue Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih416-b2020-revE.dts | 6 +++++- arch/arm/boot/dts/stih416-b2020.dts | 6 ++++++ arch/arm/boot/dts/stih416.dtsi | 14 ++++++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts b/arch/arm/boot/dts/stih416-b2020-revE.dts index a874570..047f14d 100644 --- a/arch/arm/boot/dts/stih416-b2020-revE.dts +++ b/arch/arm/boot/dts/stih416-b2020-revE.dts @@ -32,6 +32,10 @@ ethernet1: ethernet@fef08000 { snps,reset-gpio = <&PIO0 7>; }; - }; + miphy365x_phy: miphy365x@fe382000 { + st,pcie-tx-pol-inv; + st,sata-gen = <3>; + }; + }; }; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts index 276f28d..172f222 100644 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ b/arch/arm/boot/dts/stih416-b2020.dts @@ -13,4 +13,10 @@ model = "STiH416 B2020"; compatible = "st,stih416", "st,stih416-b2020"; + soc { + miphy365x_phy: miphy365x@fe382000 { + st,pcie-tx-pol-inv; + st,sata-gen = <3>; + }; + }; }; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 226d3a9..4f7d3ff 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,8 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" + +#include #include #include / { @@ -191,5 +193,17 @@ clock-names = "stmmaceth"; clocks = <&CLK_S_ICN_REG_0>; }; + + miphy365x_phy: miphy365x@fe382000 { + compatible = "st,miphy365x-phy"; + reg = <0xfe382000 0x100>, + <0xfe38a000 0x100>, + <0xfe394000 0x100>, + <0xfe804000 0x100>; + reg-names = "sata0", "sata1", "pcie0", "pcie1"; + + #phy-cells = <2>; + st,syscfg = <&syscfg_rear>; + }; }; };