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[2001:770:15f::2]) by mx.google.com with ESMTPS id t6si19174665wjq.152.2014.02.25.22.00.29 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 25 Feb 2014 22:00:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIXWq-0008V9-O5; Wed, 26 Feb 2014 05:59:37 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIXWg-0002Ah-Lr; Wed, 26 Feb 2014 05:59:26 +0000 Received: from mail-pa0-x235.google.com ([2607:f8b0:400e:c03::235]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIXWT-00029K-GD for linux-arm-kernel@lists.infradead.org; Wed, 26 Feb 2014 05:59:15 +0000 Received: by mail-pa0-f53.google.com with SMTP id ld10so309919pab.40 for ; Tue, 25 Feb 2014 21:58:51 -0800 (PST) X-Received: by 10.68.66.103 with SMTP id e7mr4493527pbt.120.1393394331220; Tue, 25 Feb 2014 21:58:51 -0800 (PST) Received: from localhost.localdomain ([14.140.2.178]) by mx.google.com with ESMTPSA id f5sm159273418pat.11.2014.02.25.21.58.47 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 25 Feb 2014 21:58:50 -0800 (PST) From: mohun106@gmail.com To: Catalin.Marinas@arm.com, will.deacon@arm.com Subject: [RFC PATCH 1/1] arm64: Add support for 48-bit Physical Address Date: Wed, 26 Feb 2014 11:28:30 +0530 Message-Id: <1393394310-6138-2-git-send-email-mohun106@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1393394310-6138-1-git-send-email-mohun106@gmail.com> References: <1393394310-6138-1-git-send-email-mohun106@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140226_005913_732241_E93DD4CF X-CRM114-Status: GOOD ( 11.80 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (mohun106[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (mohun106[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Radha Mohan Chintakuntla , linux-arm-kernel@lists.infradead.org, pkapoor@caviumnetworks.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Original-Sender: mohun106@gmail.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c03::230 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=neutral (bad format) header.i=@gmail.com; dmarc=fail (p=NONE dis=NONE) header.from=gmail.com Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Radha Mohan Chintakuntla Added support for ARMv8 platforms that have 48-bit physical address implemented. There is no change in the VA bits and levels of translation. Signed-off-by: Radha Mohan Chintakuntla --- arch/arm64/Kconfig | 3 +++ arch/arm64/include/asm/kvm_arm.h | 9 ++++++++- arch/arm64/include/asm/pgtable-hwdef.h | 15 +++++++++++++++ arch/arm64/mm/proc.S | 2 +- 4 files changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 27bbcfc..4494327 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -106,6 +106,9 @@ config IOMMU_HELPER config KERNEL_MODE_NEON def_bool y +config ARCH_SUPPORTS_48BIT_PA + def_bool n + source "init/Kconfig" source "kernel/Kconfig.freezer" diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 0eb3986..214b12d 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -107,6 +107,7 @@ /* VTCR_EL2 Registers bits */ #define VTCR_EL2_PS_MASK (7 << 16) #define VTCR_EL2_PS_40B (2 << 16) +#define VTCR_EL2_PS_48B (5 << 16) #define VTCR_EL2_TG0_MASK (1 << 14) #define VTCR_EL2_TG0_4K (0 << 14) #define VTCR_EL2_TG0_64K (1 << 14) @@ -121,6 +122,12 @@ #define VTCR_EL2_T0SZ_MASK 0x3f #define VTCR_EL2_T0SZ_40B 24 +#ifdef CONFIG_ARCH_SUPPORTS_48BIT_PA +#define VTCR_EL2_PS_BITS VTCR_EL2_PS_48B +#else +#define VTCR_EL2_PS_BITS VTCR_EL2_PS_40B +#endif + #ifdef CONFIG_ARM64_64K_PAGES /* * Stage2 translation configuration: @@ -129,7 +136,7 @@ * 64kB pages (TG0 = 1) * 2 level page tables (SL = 1) */ -#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \ +#define VTCR_EL2_FLAGS (VTCR_EL2_PS_BITS | VTCR_EL2_TG0_64K | \ VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ VTCR_EL2_T0SZ_40B) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index b1d2e26..6d93ba6 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -99,10 +99,18 @@ #define PMD_HYP PMD_SECT_USER #define PTE_HYP PTE_USER +#ifdef CONFIG_ARCH_SUPPORTS_48BIT_PA +/* + * 48-bit physical address supported. + */ +#define PHYS_MASK_SHIFT (48) +#else /* * 40-bit physical address supported. */ #define PHYS_MASK_SHIFT (40) +#endif + #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) /* @@ -123,7 +131,14 @@ #define TCR_TG0_64K (UL(1) << 14) #define TCR_TG1_64K (UL(1) << 30) #define TCR_IPS_40BIT (UL(2) << 32) +#define TCR_IPS_48BIT (UL(5) << 32) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) +#ifdef CONFIG_ARCH_SUPPORTS_48BIT_PA +#define TCR_IPS_BITS TCR_IPS_48BIT +#else +#define TCR_IPS_BITS TCR_IPS_40BIT +#endif + #endif diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 1333e6f..3d573a6 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -215,7 +215,7 @@ ENTRY(__cpu_setup) * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for * both user and kernel. */ - ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \ + ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_BITS | \ TCR_ASID16 | TCR_TBI0 | (1 << 31) #ifdef CONFIG_ARM64_64K_PAGES orr x10, x10, TCR_TG0_64K