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[188.246.204.87]) by mx.google.com with ESMTPSA id f3sm43028211wiv.2.2014.02.18.07.27.37 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Feb 2014 07:27:38 -0800 (PST) From: Steve Capper To: linux-arm-kernel@lists.infradead.org, linux@arm.linux.org.uk, linux-mm@kvack.org Subject: [PATCH 5/5] arm: mm: Add Transparent HugePage support for non-LPAE Date: Tue, 18 Feb 2014 15:27:15 +0000 Message-Id: <1392737235-27286-6-git-send-email-steve.capper@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1392737235-27286-1-git-send-email-steve.capper@linaro.org> References: <1392737235-27286-1-git-send-email-steve.capper@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140218_152800_420645_59ABEB67 X-CRM114-Status: GOOD ( 17.31 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on casper.infradead.org summary: Content analysis details: (-2.6 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.169 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Steve Capper , arnd@arndb.de, catalin.marinas@arm.com, will.deacon@arm.com, dsaxena@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: steve.capper@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Much of the required code for THP has been implemented in the earlier non-LPAE HugeTLB patch. One more domain bit is used (to store whether or not the THP is splitting). Some THP helper functions are defined; and we have to re-define pmd_page such that it distinguishes between page tables and sections. Signed-off-by: Steve Capper --- arch/arm/Kconfig | 2 +- arch/arm/include/asm/pgtable-2level.h | 32 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/pgtable-3level.h | 1 + arch/arm/include/asm/pgtable.h | 2 -- arch/arm/include/asm/tlb.h | 3 +++ 5 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 58b17b1..48dc4b5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1820,7 +1820,7 @@ config SYS_SUPPORTS_HUGETLBFS config HAVE_ARCH_TRANSPARENT_HUGEPAGE def_bool y - depends on ARM_LPAE + depends on SYS_SUPPORTS_HUGETLBFS config ARCH_WANT_GENERAL_HUGETLB def_bool y diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 1fb2050..0882d77 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -211,6 +211,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) */ #define PMD_DSECT_DIRTY (_AT(pmdval_t, 1) << 5) #define PMD_DSECT_AF (_AT(pmdval_t, 1) << 6) +#define PMD_DSECT_SPLITTING (_AT(pmdval_t, 1) << 7) #define PMD_BIT_FUNC(fn,op) \ static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; } @@ -235,6 +236,16 @@ extern pgprot_t get_huge_pgprot(pgprot_t newprot); #define pfn_pmd(pfn,prot) __pmd(__pfn_to_phys(pfn) | pgprot_val(prot)); #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),get_huge_pgprot(prot)); +#define pmd_mkhuge(pmd) (pmd) + +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_DSECT_SPLITTING) +#define pmd_trans_huge(pmd) (pmd_thp_or_huge(pmd)) +#else +static inline int pmd_trans_huge(pmd_t pmd); +#endif + +#define pmd_mknotpresent(pmd) (__pmd(0)) PMD_BIT_FUNC(mkdirty, |= PMD_DSECT_DIRTY); PMD_BIT_FUNC(mkwrite, |= PMD_SECT_AP_WRITE); @@ -242,6 +253,8 @@ PMD_BIT_FUNC(wrprotect, &= ~PMD_SECT_AP_WRITE); PMD_BIT_FUNC(mknexec, |= PMD_SECT_XN); PMD_BIT_FUNC(rmprotnone, |= PMD_TYPE_SECT); PMD_BIT_FUNC(mkyoung, |= PMD_DSECT_AF); +PMD_BIT_FUNC(mkold, &= ~PMD_DSECT_AF); +PMD_BIT_FUNC(mksplitting, |= PMD_DSECT_SPLITTING); #define pmd_young(pmd) (pmd_val(pmd) & PMD_DSECT_AF) #define pmd_write(pmd) (pmd_val(pmd) & PMD_SECT_AP_WRITE) @@ -282,6 +295,25 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) return pmd; } +static inline int has_transparent_hugepage(void) +{ + return 1; +} + +static inline struct page *pmd_page(pmd_t pmd) +{ + /* + * for a section, we need to mask off more of the pmd + * before looking up the page as it is a section descriptor. + * + * pmd_page only gets sections from the thp code. + */ + if (pmd_trans_huge(pmd)) + return (phys_to_page(pmd_val(pmd) & HPAGE_MASK)); + + return phys_to_page(pmd_val(pmd) & PHYS_MASK); +} + #endif /* __ASSEMBLY__ */ #endif /* _ASM_PGTABLE_2LEVEL_H */ diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index c1c8b37..aa2683f 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -211,6 +211,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) #define pmd_hugewillfault(pmd) (!pmd_young(pmd) || !pmd_write(pmd)) #define pmd_thp_or_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) +#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) #ifdef CONFIG_TRANSPARENT_HUGEPAGE #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 9cc40bc..3675c63 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -189,8 +189,6 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); } -#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) - #ifndef CONFIG_HIGHPTE #define __pte_map(pmd) pmd_page_vaddr(*(pmd)) #define __pte_unmap(pte) do { } while (0) diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index b2498e6..77037d9 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h @@ -218,6 +218,9 @@ static inline void tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr) { tlb_add_flush(tlb, addr); +#ifndef CONFIG_ARM_LPAE + tlb_add_flush(tlb, addr + SZ_1M); +#endif } #define pte_free_tlb(tlb, ptep, addr) __pte_free_tlb(tlb, ptep, addr)