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[128.107.239.233]) by mx.google.com with ESMTPSA id tr7sm63581349oec.0.2014.02.11.21.58.21 for (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128/128); Tue, 11 Feb 2014 21:58:23 -0800 (PST) From: Victor Kamensky To: kvmarm@lists.cs.columbia.edu, marc.zyngier@arm.com, christoffer.dall@linaro.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/5] ARM64: KVM: fix vgic_bitmap_get_reg function for BE 64bit case Date: Tue, 11 Feb 2014 21:57:23 -0800 Message-Id: <1392184643-6108-6-git-send-email-victor.kamensky@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1392184643-6108-1-git-send-email-victor.kamensky@linaro.org> References: <1392184643-6108-1-git-send-email-victor.kamensky@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140212_005845_252870_664EABC9 X-CRM114-Status: GOOD ( 11.79 ) X-Spam-Score: 0.4 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.219.54 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linaro-kernel@lists.linaro.org, Victor Kamensky , taras.kondratiuk@linaro.org, will.deacon@arm.com, andre.przywara@linaro.org, ben.dooks@codethink.co.uk, Dave.Martin@arm.com, rmk@arm.linux.org.uk X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: victor.kamensky@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Fix vgic_bitmap_get_reg function to return 'right' word address of 'unsigned long' bitmap value in case of BE 64bit image. Signed-off-by: Victor Kamensky --- virt/kvm/arm/vgic.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 7e11458..e56c5f8 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -96,14 +96,37 @@ static u32 vgic_nr_lr; static unsigned int vgic_maint_irq; +/* + * struct vgic_bitmap is union that provides two view of + * the same data. In one case it is array of registers of + * u32 type (.reg). And in another it is bitmap, which is + * array of 'unsgined long' (.reg_ul). It works all well in + * case of 32bit (u32 and 'unsigned long' have the same size). + * It works ok in 64bit LE case, where 'unsigned long' + * size is 8 bytes, while u32 is 4 bytes, and least siginificant + * word of 'unsigned long' matches lower index of .reg array. + * It breaks in 64bit BE case. In this case word sized + * register of even index actually resides in least significant + * word of 'unsigned long' which has address at offset plus 4 + * bytes. And word sized register of odd index resides at most + * significant of 'unsigned long' which has offset minus 4 + * bytes. Define REG_OFFSET_SWIZZLE that would help to + * change offset of register in case of BE 64bit system. + */ +#if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 +#define REG_OFFSET_SWIZZLE 1 +#else +#define REG_OFFSET_SWIZZLE 0 +#endif + static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset) { offset >>= 2; if (!offset) - return x->percpu[cpuid].reg; + return x->percpu[cpuid].reg + (offset^REG_OFFSET_SWIZZLE); else - return x->shared.reg + offset - 1; + return x->shared.reg + ((offset - 1)^REG_OFFSET_SWIZZLE); } static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,