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[2001:770:15f::2]) by mx.google.com with ESMTPS id hp9si7411327wib.71.2014.02.05.05.37.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Feb 2014 05:37:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WB2cj-0008Lj-Ov; Wed, 05 Feb 2014 13:34:42 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WB2bg-0002WX-78; Wed, 05 Feb 2014 13:33:36 +0000 Received: from fw-tnat.austin.arm.com ([217.140.110.23] helo=collaborate-mta1.arm.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WB2Zo-0002H4-SZ for linux-arm-kernel@lists.infradead.org; Wed, 05 Feb 2014 13:31:53 +0000 Received: from e102391-lin.cambridge.arm.com (e102391-lin.cambridge.arm.com [10.1.209.166]) by collaborate-mta1.arm.com (Postfix) with ESMTP id 8A3BB1401CD; Wed, 5 Feb 2014 07:31:07 -0600 (CST) From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Subject: [PATCH 16/18] arm64: KVM: move hcr_el2 setting into vgic-v2-switch.S Date: Wed, 5 Feb 2014 13:30:48 +0000 Message-Id: <1391607050-540-17-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1391607050-540-1-git-send-email-marc.zyngier@arm.com> References: <1391607050-540-1-git-send-email-marc.zyngier@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140205_083141_301614_23F2AB6F X-CRM114-Status: UNSURE ( 7.27 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.4 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: catalin.marinas@arm.com, will.deacon@arm.com, Christoffer Dall X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: marc.zyngier@arm.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.48 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 GICv3 requires the hcr_el2 switch to be tightly coupled with some of the interrupt controller's register switch. In order to have similar code paths, start moving the hcr_el2 manipulation code to the GICv2 switch code. Acked-by: Catalin Marinas Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp.S | 7 ------- arch/arm64/kvm/vgic-v2-switch.S | 8 ++++++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index 5a868c0..20a58fe 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.S @@ -335,11 +335,6 @@ .endm .macro activate_traps - ldr x2, [x0, #VCPU_IRQ_LINES] - ldr x1, [x0, #VCPU_HCR_EL2] - orr x2, x2, x1 - msr hcr_el2, x2 - ldr x2, =(CPTR_EL2_TTA) msr cptr_el2, x2 @@ -353,8 +348,6 @@ .endm .macro deactivate_traps - mov x2, #HCR_RW - msr hcr_el2, x2 msr cptr_el2, xzr msr hstr_el2, xzr diff --git a/arch/arm64/kvm/vgic-v2-switch.S b/arch/arm64/kvm/vgic-v2-switch.S index c5dc777..d36cd7a 100644 --- a/arch/arm64/kvm/vgic-v2-switch.S +++ b/arch/arm64/kvm/vgic-v2-switch.S @@ -85,6 +85,9 @@ CPU_BE( rev w5, w5 ) sub w4, w4, #1 cbnz w4, 1b 2: + mov x2, #HCR_RW + msr hcr_el2, x2 + isb .endm /* @@ -92,6 +95,11 @@ CPU_BE( rev w5, w5 ) * x0: Register pointing to VCPU struct */ .macro restore_vgic_v2_state + ldr x2, [x0, #VCPU_IRQ_LINES] + ldr x1, [x0, #VCPU_HCR_EL2] + orr x2, x2, x1 + msr hcr_el2, x2 + /* Get VGIC VCTRL base into x2 */ ldr x2, [x0, #VCPU_KVM] kern_hyp_va x2