From patchwork Wed Jan 8 13:47:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 22960 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f197.google.com (mail-ob0-f197.google.com [209.85.214.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id C8937202E2 for ; Wed, 8 Jan 2014 13:49:03 +0000 (UTC) Received: by mail-ob0-f197.google.com with SMTP id vb8sf6102713obc.4 for ; Wed, 08 Jan 2014 05:49:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=nPC7yCMJJVi3CounU1Y0uQmhqu274isM/8Wh2fvfU1w=; b=NVOuCZoqbZDemaXpfJ/fopswNZQdiBpEINNleLz2QixtCoiTQPELOck8hS5fK6ksJk ewyMcjRfUkxo+EIeWLQGNf6I60KrelUmX2u8VBoNqmBecOJ/VkRW6byHHJ6El12l30Fm dAAnwamXrJ1fntXg35aN0iBDZIuJnowscSPFQ6AQNYWRlZLYQQ5IP1wIPPUYV+31LFHI X31+bmKfBVu9NHz5IzxrdVabPSQrwNceVC6KZ14iUFAYJtuwtr8AJntag9oHDND4Q095 oWtD3CVVV3gy6ZT+eUPdOIlWGGUB/aP1N9SckNBaSv0156JgxKRZSQ6LBzqFvOm4vWaL 0X1A== X-Gm-Message-State: ALoCoQkzkDKAJ3O+RyTeriAOllqPStY7St5BaWj3/MIIjPEJzglm/9MgTnBsuvQNgq/+aVGrHSay X-Received: by 10.50.47.18 with SMTP id z18mr15718377igm.1.1389188942916; Wed, 08 Jan 2014 05:49:02 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.4.105 with SMTP id j9ls585706qej.94.gmail; Wed, 08 Jan 2014 05:49:02 -0800 (PST) X-Received: by 10.52.230.35 with SMTP id sv3mr7511294vdc.27.1389188942821; Wed, 08 Jan 2014 05:49:02 -0800 (PST) Received: from mail-ve0-f182.google.com (mail-ve0-f182.google.com [209.85.128.182]) by mx.google.com with ESMTPS id ef6si611137ved.47.2014.01.08.05.49.02 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 Jan 2014 05:49:02 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.182; Received: by mail-ve0-f182.google.com with SMTP id jy13so1271254veb.13 for ; Wed, 08 Jan 2014 05:49:02 -0800 (PST) X-Received: by 10.52.187.232 with SMTP id fv8mr2560713vdc.60.1389188942669; Wed, 08 Jan 2014 05:49:02 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.59.13.131 with SMTP id ey3csp226635ved; Wed, 8 Jan 2014 05:49:02 -0800 (PST) X-Received: by 10.180.36.231 with SMTP id t7mr21801354wij.40.1389188941672; Wed, 08 Jan 2014 05:49:01 -0800 (PST) Received: from mail-wg0-f45.google.com (mail-wg0-f45.google.com [74.125.82.45]) by mx.google.com with ESMTPS id mc2si5277532wjb.161.2014.01.08.05.49.01 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 Jan 2014 05:49:01 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.45 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=74.125.82.45; Received: by mail-wg0-f45.google.com with SMTP id y10so1442818wgg.0 for ; Wed, 08 Jan 2014 05:49:01 -0800 (PST) X-Received: by 10.194.171.34 with SMTP id ar2mr10938618wjc.81.1389188941124; Wed, 08 Jan 2014 05:49:01 -0800 (PST) Received: from localhost.localdomain (cpc15-aztw25-2-0-cust493.aztw.cable.virginm.net. [92.233.57.238]) by mx.google.com with ESMTPSA id j9sm48125217wjx.18.2014.01.08.05.48.59 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 Jan 2014 05:49:00 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: computersforpeace@gmail.com, angus.clark@st.com, Lee Jones Subject: [PATCH v4 24/37] mtd: st_spi_fsm: Supply the N25Qxxx chip specific configuration call-back Date: Wed, 8 Jan 2014 13:47:07 +0000 Message-Id: <1389188840-14306-25-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1389188840-14306-1-git-send-email-lee.jones@linaro.org> References: <1389188840-14306-1-git-send-email-lee.jones@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In the FSM driver we handle chip differences by providing the possibility of calling back into a chip specific initialisation routine. In this patch we provide one for the N25Qxxx series, which endeavours to setup things like the read, write and erase sequences, as they differ from the default. We also configure 32bit support and the amount of dummy cycles to use. Signed-off-by: Lee Jones --- drivers/mtd/devices/st_spi_fsm.c | 84 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 3b56b6e..28d8ac0 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -310,6 +310,8 @@ struct flash_info { int (*config)(struct stfsm *); }; +static int stfsm_n25q_config(struct stfsm *fsm); + static struct flash_info flash_types[] = { /* * ST Microelectronics/Numonyx -- @@ -352,9 +354,10 @@ static struct flash_info flash_types[] = { FLASH_FLAG_WRITE_1_2_2 | \ FLASH_FLAG_WRITE_1_1_4 | \ FLASH_FLAG_WRITE_1_4_4) - { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, NULL }, + { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, + stfsm_n25q_config }, { "n25q256", 0x20ba19, 0, 64 * 1024, 512, - N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, NULL }, + N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config }, /* * Spansion S25FLxxxP @@ -491,6 +494,8 @@ static struct seq_rw_config n25q_read4_configs[] = { {0x00, 0, 0, 0, 0, 0x00, 0, 0}, }; +static struct stfsm_seq stfsm_seq_read; /* Dynamically populated */ +static struct stfsm_seq stfsm_seq_write; /* Dynamically populated */ static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */ static struct stfsm_seq stfsm_seq_read_jedec = { @@ -833,6 +838,71 @@ static int stfsm_search_prepare_rw_seq(struct stfsm *fsm, return 0; } +static int stfsm_n25q_config(struct stfsm *fsm) +{ + uint32_t flags = fsm->info->flags; + uint8_t vcr; + int ret = 0; + bool soc_reset; + + /* Configure 'READ' sequence */ + if (flags & FLASH_FLAG_32BIT_ADDR) + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + n25q_read4_configs); + else + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read, + n25q_read3_configs); + if (ret) { + dev_err(fsm->dev, + "failed to prepare READ sequence with flags [0x%08x]\n", + flags); + return ret; + } + + /* Configure 'WRITE' sequence (default configs) */ + ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write, + default_write_configs); + if (ret) { + dev_err(fsm->dev, + "preparing WRITE sequence using flags [0x%08x] failed\n", + flags); + return ret; + } + + /* * Configure 'ERASE_SECTOR' sequence */ + stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); + + /* Configure 32-bit address support */ + if (flags & FLASH_FLAG_32BIT_ADDR) { + stfsm_n25q_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr); + + soc_reset = stfsm_can_handle_soc_reset(fsm); + if (soc_reset || !fsm->booted_from_spi) { + /* + * If we can handle SoC resets, we enable 32-bit + * address mode pervasively + */ + stfsm_enter_32bit_addr(fsm, 1); + } else { + /* + * If not, enable/disable for WRITE and ERASE + * operations (READ uses special commands) + */ + fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR | + CFG_ERASESEC_TOGGLE_32BIT_ADDR); + } + } + + /* + * Configure device to use 8 dummy cycles + */ + vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED | + N25Q_VCR_WRAP_CONT); + stfsm_wrvcr(fsm, vcr); + + return 0; +} + static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec) { const struct stfsm_seq *seq = &stfsm_seq_read_jedec; @@ -1075,6 +1145,16 @@ static int stfsm_probe(struct platform_device *pdev) fsm->info = info; + /* + * Configure READ/WRITE/ERASE sequences according to platform and + * device flags. + */ + if (info->config) { + ret = info->config(fsm); + if (ret) + return ret; + } + platform_set_drvdata(pdev, fsm); stfsm_fetch_platform_configs(pdev);