From patchwork Tue Dec 3 16:41:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 21991 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f71.google.com (mail-qa0-f71.google.com [209.85.216.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 75BE9202AE for ; Tue, 3 Dec 2013 16:41:52 +0000 (UTC) Received: by mail-qa0-f71.google.com with SMTP id o15sf14341359qap.10 for ; Tue, 03 Dec 2013 08:41:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=lvuvPoYnqKcaQL9Mv3P61N+m7Zyf/JigU8htz4yPujo=; b=Sm+pFmHc9havqjt1oAhNbHtLDciQn35NqnzZ/j2cMrz+g5ocRE+P+kkmjpazXWuZyr OHrvES+TK5iQfRO5ujLBrG4DYFDvRrhRK5hkjyYsUB8nYjDci3WZ7x6Zm4cRxf/VXXLD xubmY6qGvcy4L26SBdJpceCel16t8cooAKn9CDL/FdBlcfWOfdTLcBMe8QzssVFkLlJz gAG/imwzF7oQJ3Me2WfvcwIEZ8fn5VCyjQ0xRA/GvtsWXTjzoACfF1IeOxys8sTTG/T3 i0IZPWPbfPRN1EZ+ONksaR3f9w3oO3DB1FBrV/77tQCqlMT5sz+Q90IgwP33oPF7nZdP x7iw== X-Gm-Message-State: ALoCoQnTAj435xYusAyROLD9Lf2IrhfrjJltPe9g62GVxoo4RUDdmNKp4oy6AXxTo/2wuub36yEl X-Received: by 10.236.32.74 with SMTP id n50mr35364267yha.13.1386088912224; Tue, 03 Dec 2013 08:41:52 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.82.49 with SMTP id f17ls4604235qey.54.gmail; Tue, 03 Dec 2013 08:41:52 -0800 (PST) X-Received: by 10.58.118.36 with SMTP id kj4mr4522957veb.2.1386088912112; Tue, 03 Dec 2013 08:41:52 -0800 (PST) Received: from mail-ve0-f178.google.com (mail-ve0-f178.google.com [209.85.128.178]) by mx.google.com with ESMTPS id tj7si12814678vdc.33.2013.12.03.08.41.52 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Dec 2013 08:41:52 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.178; Received: by mail-ve0-f178.google.com with SMTP id c14so10531429vea.37 for ; Tue, 03 Dec 2013 08:41:52 -0800 (PST) X-Received: by 10.58.50.194 with SMTP id e2mr115185veo.54.1386088911958; Tue, 03 Dec 2013 08:41:51 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp222723vcz; Tue, 3 Dec 2013 08:41:51 -0800 (PST) X-Received: by 10.67.5.233 with SMTP id cp9mr7348255pad.147.1386088911094; Tue, 03 Dec 2013 08:41:51 -0800 (PST) Received: from mail-pb0-f49.google.com (mail-pb0-f49.google.com [209.85.160.49]) by mx.google.com with ESMTPS id ez5si32568718pab.222.2013.12.03.08.41.50 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Dec 2013 08:41:51 -0800 (PST) Received-SPF: neutral (google.com: 209.85.160.49 is neither permitted nor denied by best guess record for domain of hanjun.guo@linaro.org) client-ip=209.85.160.49; Received: by mail-pb0-f49.google.com with SMTP id jt11so21358783pbb.22 for ; Tue, 03 Dec 2013 08:41:50 -0800 (PST) X-Received: by 10.66.118.71 with SMTP id kk7mr76477533pab.14.1386088910553; Tue, 03 Dec 2013 08:41:50 -0800 (PST) Received: from localhost ([61.148.199.138]) by mx.google.com with ESMTPSA id om6sm41401605pbc.43.2013.12.03.08.41.37 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 03 Dec 2013 08:41:49 -0800 (PST) From: Hanjun Guo To: "Rafael J. Wysocki" , Catalin Marinas , Will Deacon , Russell King - ARM Linux , Daniel Lezcano Cc: linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Grant Likely , Matthew Garrett , Olof Johansson , Linus Walleij , Bjorn Helgaas , Rob Herring , Mark Rutland , Jon Masters , patches@linaro.org, linux-kernel@vger.kernel.org, linaro-kernel@lists.linaro.org, linaro-acpi@lists.linaro.org, Hanjun Guo Subject: [RFC part3 PATCH 0/2] Using ACPI GTDT table to initialize arch timer Date: Wed, 4 Dec 2013 00:41:29 +0800 Message-Id: <1386088891-2917-1-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: hanjun.guo@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This is the last part of patch set for core of ARM64 ACPI, and is based on the patch set part2 "Using ACPI MADT table to initialise SMP and GIC". ACPI GTDT (Generic Timer Description Table) is used for ARM/ARM64 only, and contains the information for arch timer initialisation. This patch trys to convert the arch timer to ACPI using GTDT. After this patch set was posted, we already finished the SMP, GIC and arch timer initialisation, which all are essential for ARM64 core system running, then we will focus on converting the device drivers to ACPI. Here is the GTDT ASL code I used: --- platforms/foundation-v8.acpi/gtdt.asl | 35 ++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 12 deletions(-) Hanjun Guo (2): clocksource / arch_timer: Use ACPI GTDT table to initialize arch timer ARM64 / clocksource: Use arch_timer_acpi_init() arch/arm64/kernel/time.c | 4 ++ drivers/clocksource/arm_arch_timer.c | 129 ++++++++++++++++++++++++++++++---- include/clocksource/arm_arch_timer.h | 7 +- 3 files changed, 124 insertions(+), 16 deletions(-) diff --git a/platforms/foundation-v8.acpi/gtdt.asl b/platforms/foundation-v8.acpi/gtdt.asl index 18c821a..714d61c 100644 --- a/platforms/foundation-v8.acpi/gtdt.asl +++ b/platforms/foundation-v8.acpi/gtdt.asl @@ -1,5 +1,6 @@ /* * Copyright (c) 2013, Al Stone + * Hanjun Guo * * [GTDT] Generic Timer Description Table * Format: [ByteLength] FieldName : HexFieldValue @@ -21,22 +22,32 @@ [0004] Flags (decoded below) : 00000001 Memory Present : 1 -[0004] Secure PL1 Interrupt : 00000000 -[0004] SPL1 Flags (decoded below) : 00000000 - Trigger Mode : 0 +/* In Foundation model's dts file, the last cell of interrupts + * is 0xff01, it means its cpu mask is FF, and trigger type + * and flag is 1 = low-to-high edge triggered. + * + * so in ACPI the Trigger Mode is 1 - Edge triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * using direct mapping for hwirqs, it means that we using + * ID [16, 31] for PPI, not [0, 15] used in FDT. + */ +[0004] Secure PL1 Interrupt : 0000001d +[0004] SPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -[0004] Non-Secure PL1 Interrupt : 00000000 -[0004] NSPL1 Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Non-Secure PL1 Interrupt : 0000001e +[0004] NSPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -[0004] Virtual Timer Interrupt : 00000000 -[0004] VT Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Virtual Timer Interrupt : 0000001b +[0004] VT Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -[0004] Non-Secure PL2 Interrupt : 00000000 -[0004] NSPL2 Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Non-Secure PL2 Interrupt : 0000001a +[0004] NSPL2 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0