From patchwork Thu Nov 21 12:59:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 21663 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f70.google.com (mail-yh0-f70.google.com [209.85.213.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id F146120E7C for ; Thu, 21 Nov 2013 12:59:12 +0000 (UTC) Received: by mail-yh0-f70.google.com with SMTP id l109sf6353867yhq.9 for ; Thu, 21 Nov 2013 04:59:12 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=nrJVhXGaa/1CAdkQxKj2D27gtkRxPybDILFOvAzBPxE=; b=gL/PxuDz5MOw8BhBLlTztwKfLX3oGhy9SJdmLBUQ/cu1/1mYjXea0uRQ0aa03+dAUu YX9OqI3ZLH51t8Luh6jqAqkYR4PcR7ULOHNdyKqpdFJWBlG8/CcIlG6BjRpwbil3xGvS xrwdfrPQkuSP6SxFejL61G16dteCbMeHOW0NsR/8mMD/78XKRQ664iN51rJyYAgLY6ye LEPNzyu/c/0JQT0NQYNHNRi1wsd5GzGFp/wfkJlcvCyy7WrpxUhRH/DhQZGZH3nh2fFn pgTv1nFDKDQn/OrOUidp5sbPfqTzxnk1AcK9ZGx5lKZpH/IIvu6590JzyOE5FnXNJQWV U0nQ== X-Gm-Message-State: ALoCoQmn5R4r/4iQ76yIu+lKKI0fA4Kzb6S5GIcm7sAlplzbHPkGrFvGIgREJfF1VHnOvRdbcSah X-Received: by 10.52.34.234 with SMTP id c10mr1802995vdj.5.1385038752764; Thu, 21 Nov 2013 04:59:12 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.81.229 with SMTP id d5ls464656qey.64.gmail; Thu, 21 Nov 2013 04:59:12 -0800 (PST) X-Received: by 10.220.58.1 with SMTP id e1mr5871559vch.0.1385038752666; Thu, 21 Nov 2013 04:59:12 -0800 (PST) Received: from mail-vb0-f42.google.com (mail-vb0-f42.google.com [209.85.212.42]) by mx.google.com with ESMTPS id ph5si10940978veb.90.2013.11.21.04.59.12 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 21 Nov 2013 04:59:12 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.42 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.42; Received: by mail-vb0-f42.google.com with SMTP id w18so1465305vbj.1 for ; Thu, 21 Nov 2013 04:59:12 -0800 (PST) X-Received: by 10.52.103.35 with SMTP id ft3mr4964050vdb.5.1385038752569; Thu, 21 Nov 2013 04:59:12 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp426157vcz; Thu, 21 Nov 2013 04:59:12 -0800 (PST) X-Received: by 10.180.208.4 with SMTP id ma4mr5635817wic.43.1385038751395; Thu, 21 Nov 2013 04:59:11 -0800 (PST) Received: from mail-wi0-f175.google.com (mail-wi0-f175.google.com [209.85.212.175]) by mx.google.com with ESMTPS id wx3si11193617wjb.102.2013.11.21.04.59.11 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 21 Nov 2013 04:59:11 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.175 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=209.85.212.175; Received: by mail-wi0-f175.google.com with SMTP id hi5so3777411wib.14 for ; Thu, 21 Nov 2013 04:59:10 -0800 (PST) X-Received: by 10.194.104.42 with SMTP id gb10mr5475388wjb.16.1385038750899; Thu, 21 Nov 2013 04:59:10 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id bk7sm5270612wib.10.2013.11.21.04.59.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Nov 2013 04:59:10 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Roland Stigge Cc: Linus Walleij Subject: [PATCH 2/2] ARM: lpc32xx: move custom GPIO header Date: Thu, 21 Nov 2013 13:59:04 +0100 Message-Id: <1385038744-9780-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.42 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Move to . Cc: Roland Stigge Signed-off-by: Linus Walleij --- Roland: can you please ACK this patch so I can take this through the GPIO tree? BTW: the LPC32xx GPIO driver could use some love, so when you have the time: get rid of this platform data and break the need for altogether. Well, the driver should not really need to include any header before I'm really happy actually... --- arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h | 50 ----------------------- arch/arm/mach-lpc32xx/phy3250.c | 2 +- drivers/gpio/gpio-lpc32xx.c | 2 +- include/linux/platform_data/gpio-lpc32xx.h | 50 +++++++++++++++++++++++ 4 files changed, 52 insertions(+), 52 deletions(-) delete mode 100644 arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h create mode 100644 include/linux/platform_data/gpio-lpc32xx.h diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h deleted file mode 100644 index a544e962a818..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_GPIO_LPC32XX_H -#define __MACH_GPIO_LPC32XX_H - -/* - * Note! - * Muxed GP pins need to be setup to the GP state in the board level - * code prior to using this driver. - * GPI pins : 28xP3 group - * GPO pins : 24xP3 group - * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group - */ - -#define LPC32XX_GPIO_P0_MAX 8 -#define LPC32XX_GPIO_P1_MAX 24 -#define LPC32XX_GPIO_P2_MAX 13 -#define LPC32XX_GPIO_P3_MAX 6 -#define LPC32XX_GPI_P3_MAX 29 -#define LPC32XX_GPO_P3_MAX 24 - -#define LPC32XX_GPIO_P0_GRP 0 -#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX) -#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX) -#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX) -#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX) -#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) - -/* - * A specific GPIO can be selected with this macro - * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) - * See the LPC32x0 User's guide for GPIO group numbers - */ -#define LPC32XX_GPIO(x, y) ((x) + (y)) - -#endif /* __MACH_GPIO_LPC32XX_H */ diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index e54f87ec2e4a..34932e0e31fa 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -44,7 +45,6 @@ #include #include #include -#include #include "common.h" /* diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c index 2d5555decf0c..a7093e010149 100644 --- a/drivers/gpio/gpio-lpc32xx.c +++ b/drivers/gpio/gpio-lpc32xx.c @@ -25,10 +25,10 @@ #include #include #include +#include #include #include -#include #include #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) diff --git a/include/linux/platform_data/gpio-lpc32xx.h b/include/linux/platform_data/gpio-lpc32xx.h new file mode 100644 index 000000000000..a544e962a818 --- /dev/null +++ b/include/linux/platform_data/gpio-lpc32xx.h @@ -0,0 +1,50 @@ +/* + * Author: Kevin Wells + * + * Copyright (C) 2010 NXP Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_GPIO_LPC32XX_H +#define __MACH_GPIO_LPC32XX_H + +/* + * Note! + * Muxed GP pins need to be setup to the GP state in the board level + * code prior to using this driver. + * GPI pins : 28xP3 group + * GPO pins : 24xP3 group + * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group + */ + +#define LPC32XX_GPIO_P0_MAX 8 +#define LPC32XX_GPIO_P1_MAX 24 +#define LPC32XX_GPIO_P2_MAX 13 +#define LPC32XX_GPIO_P3_MAX 6 +#define LPC32XX_GPI_P3_MAX 29 +#define LPC32XX_GPO_P3_MAX 24 + +#define LPC32XX_GPIO_P0_GRP 0 +#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX) +#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX) +#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX) +#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX) +#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) + +/* + * A specific GPIO can be selected with this macro + * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) + * See the LPC32x0 User's guide for GPIO group numbers + */ +#define LPC32XX_GPIO(x, y) ((x) + (y)) + +#endif /* __MACH_GPIO_LPC32XX_H */