From patchwork Sun Nov 17 11:03:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 21563 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f199.google.com (mail-ob0-f199.google.com [209.85.214.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 40D8720299 for ; Sun, 17 Nov 2013 11:04:45 +0000 (UTC) Received: by mail-ob0-f199.google.com with SMTP id gq1sf1979384obb.6 for ; Sun, 17 Nov 2013 03:04:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=95FM73+f8XQuGaXYi9azrirNKea4qP3sdD+qXWW0UK0=; b=eW1zKwdcbC5H5v2oy6YJ2JElHCxYMmXrBUNcn/nvKVjl6OXoztkDnjPRhxuFG9+mD8 J9HPmtbaAgBHB7JEFc3bhFuJ29lflwYDkdrBJg//quW9VQVrlWgLl2ExuzbygyAIgZcr Vm33i//tG9+LQ5+MOk51mxuAt6gQBoGgbVhMN/Bf18mCK/M8QB6lc9eh6gB5smDGF3gQ 52ziCWDLGBItIQU7Ll40ikGvOBIA7ZFosnySKQoU761EsHsUvYIoJTU68l4ZqGkIr9+L ZAp5SbaMOT08oG0GNq5jQ+f0R1Vfc+Amae7sQftzmzelTOXD1C8XPLmKpx1ZQ5UlgdTc PB9g== X-Gm-Message-State: ALoCoQlUyAuMYQtuHaJ2Tjtm5CwO93xa8MAy25poBgq929zPCWETfTrDyoblUmJQI1KZ8wxqAiDY X-Received: by 10.182.105.227 with SMTP id gp3mr6378903obb.23.1384686284871; Sun, 17 Nov 2013 03:04:44 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.104.40 with SMTP id gb8ls1073369qeb.27.gmail; Sun, 17 Nov 2013 03:04:44 -0800 (PST) X-Received: by 10.52.28.6 with SMTP id x6mr8003000vdg.3.1384686284772; Sun, 17 Nov 2013 03:04:44 -0800 (PST) Received: from mail-vb0-f54.google.com (mail-vb0-f54.google.com [209.85.212.54]) by mx.google.com with ESMTPS id ip2si5581879vcb.41.2013.11.17.03.04.44 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 17 Nov 2013 03:04:44 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.54 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.54; Received: by mail-vb0-f54.google.com with SMTP id p6so587990vbe.13 for ; Sun, 17 Nov 2013 03:04:44 -0800 (PST) X-Received: by 10.58.39.97 with SMTP id o1mr9830816vek.15.1384686284667; Sun, 17 Nov 2013 03:04:44 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp140372vcz; Sun, 17 Nov 2013 03:04:44 -0800 (PST) X-Received: by 10.180.210.134 with SMTP id mu6mr13054884wic.37.1384686283681; Sun, 17 Nov 2013 03:04:43 -0800 (PST) Received: from mail-wg0-f47.google.com (mail-wg0-f47.google.com [74.125.82.47]) by mx.google.com with ESMTPS id tm8si4616983wjc.127.2013.11.17.03.04.43 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 17 Nov 2013 03:04:43 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.47 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=74.125.82.47; Received: by mail-wg0-f47.google.com with SMTP id y10so5162147wgg.14 for ; Sun, 17 Nov 2013 03:04:43 -0800 (PST) X-Received: by 10.180.221.106 with SMTP id qd10mr12863940wic.57.1384686283261; Sun, 17 Nov 2013 03:04:43 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id fu1sm13156973wib.8.2013.11.17.03.04.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 17 Nov 2013 03:04:42 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Lee Jones Cc: devicetree@vger.kernel.org, Linus Walleij Subject: [PATCH 07/21] ARM: ux500: move SPI pin config to device tree Date: Sun, 17 Nov 2013 12:03:56 +0100 Message-Id: <1384686250-10542-8-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1384686250-10542-1-git-send-email-linus.walleij@linaro.org> References: <1384686250-10542-1-git-send-email-linus.walleij@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.54 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This moves the SPI pin control table out of the board file and into the device tree. Move the specific setting for SSP0 on the HREFprev60 into the prev60-specific DTS file. The SPI2 configuration is not really connected to any device, as it will conflict with GPIO218 which is used on all HREFs. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 61 ++++++++++++++++++++++++++ arch/arm/boot/dts/ste-hrefprev60.dtsi | 22 ++++++++++ arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi | 31 +++++++++++++ arch/arm/mach-ux500/board-mop500-pins.c | 19 -------- 4 files changed, 114 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index 6868fec95d64..ec990d8e1029 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -215,6 +215,67 @@ }; }; + /* Settings for all SPI default and sleep states */ + spi2 { + spi2_default_mode: spi_default { + default_mux { + ste,function = "spi2"; + ste,pins = "spi2_oc1_2"; + }; + default_cfg1 { + ste,pins = "GPIO216_AG12"; /* FRM */ + ste,config = <&gpio_out_hi>; + }; + default_cfg2 { + ste,pins = "GPIO218_AH11"; /* RXD */ + ste,config = <&in_pd>; + }; + default_cfg3 { + ste,pins = + "GPIO215_AH13", /* TXD */ + "GPIO217_AH12"; /* CLK */ + ste,config = <&out_lo>; + }; + }; + + spi2_idle_mode: spi_idle { + /* + * The idle mode is basically sleep mode sans wakeups. Also + * note that we have muxes the pins off the function here + * as we do not state any muxing. + */ + idle_cfg1 { + ste,pins = "GPIO218_AH11"; /* RXD */ + ste,config = <&slpm_in_pdis>; + }; + idle_cfg2 { + ste,pins = "GPIO215_AH13"; /* TXD */ + ste,config = <&slpm_out_lo_pdis>; + }; + idle_cfg3 { + ste,pins = "GPIO217_AH12"; /* CLK */ + ste,config = <&slpm_pdis>; + }; + }; + + spi2_sleep_mode: spi_sleep { + sleep_cfg1 { + ste,pins = + "GPIO216_AG12", /* FRM */ + "GPIO218_AH11"; /* RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = "GPIO215_AH13"; /* TXD */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + sleep_cfg3 { + ste,pins = "GPIO217_AH12"; /* CLK */ + ste,config = <&slpm_wkup_pdis>; + }; + }; + }; + /* Settings for all MMC/SD/SDIO default and sleep states */ sdi0 { /* This is the external SD card slot, 4 bits wide */ diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index 6fc94ea65ab9..32295e396ff8 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -51,6 +51,15 @@ }; }; + ssp@80002000 { + /* + * On the first generation boards, this SSP/SPI port was connected + * to the AB8500. + */ + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_hrefprev60_mode>; + }; + vmmci: regulator-gpio { gpios = <&tc3589x_gpio 18 0x4>; enable-gpio = <&tc3589x_gpio 17 0x4>; @@ -59,6 +68,19 @@ }; pinctrl { + ssp0 { + ssp0_hrefprev60_mode: ssp0_hrefprev60_default { + hrefprev60_mux { + ste,function = "ssp0"; + ste,pins = "ssp0_a_1"; + }; + hrefprev60_cfg1 { + ste,pins = "GPIO145_C13"; /* RXD */ + ste,config = <&in_pd>; + }; + + }; + }; sdi0 { /* This additional pin needed on early MOP500 and HREFs previous to v60 */ sdi0_default_mode: sdi0_default { diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi index 9f3e87573f86..456a25fbfaee 100644 --- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi @@ -41,6 +41,23 @@ ste,output = ; }; + gpio_out_hi: gpio_output_high { + ste,gpio = ; + ste,output = ; + }; + + slpm_pdis: slpm_pdis { + ste,sleep = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_wkup_pdis: slpm_wkup_pdis { + ste,sleep = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_wkup_pdis_en: slpm_wkup_pdis_en { ste,sleep = ; ste,sleep-wakeup = ; @@ -53,6 +70,13 @@ ste,sleep-wakeup = ; }; + slpm_in_pdis: slpm_in_pdis { + ste,sleep = ; + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_in_wkup_pdis: slpm_in_wkup_pdis { ste,sleep = ; ste,sleep-input = ; @@ -86,6 +110,13 @@ ste,sleep-pull-disable = ; }; + slpm_out_lo_pdis: slpm_out_lo_pdis { + ste,sleep = ; + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis { ste,sleep = ; ste,sleep-output = ; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index a6d431bd0659..8fba58c98da2 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -342,22 +342,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { /* LCD VSI1 sleep state */ DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"), - /* Mux in SPI2 pins on the "other C1" altfunction */ - DB8500_MUX("spi2_oc1_2", "spi2", "spi2"), - DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */ - DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */ - DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */ - DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */ - /* SPI2 idle state */ - DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ - DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */ - DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */ - /* SPI2 sleep state */ - DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */ - DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ - DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */ - DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */ - /* ske default state */ DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"), DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */ @@ -582,9 +566,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { * on-chip pins as the HREFv60 and later does. */ static struct pinctrl_map __initdata mop500_pinmap[] = { - /* Mux in SSP0, pull down RXD pin */ - DB8500_MUX_HOG("ssp0_a_1", "ssp0"), - DB8500_PIN_HOG("GPIO145_C13", pd), /* * XENON Flashgun on image processor GPIO (controlled from image * processor firmware), mux in these image processor GPIO lines 0