From patchwork Sun Nov 17 11:03:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 21557 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vb0-f70.google.com (mail-vb0-f70.google.com [209.85.212.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B60C820299 for ; Sun, 17 Nov 2013 11:04:27 +0000 (UTC) Received: by mail-vb0-f70.google.com with SMTP id o19sf2167194vbm.1 for ; Sun, 17 Nov 2013 03:04:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=lbzCA13filC9+p/XMbht2K+4N7zmh3FZUvyjywjeLmM=; b=Vd4w1US/hb4Wd4OYZqpVxfehew0MlCoFeDWOHGyva0PQVRO2fAXSPG5hEu3VYkOBAl bv/p11GR55++psrxl0MuaJBL3uEoIPy7HA9wscr5YGPPRFVp0YYr32GZxUovMZD0ovgx a425mut/GpwpGpiptpzfh7QGgYnIBxTodETfNWyCshCUHQ+yfY6+iQ5HX//TEhH+i4dR //FtBGoBhW8+5WAcHTb29HWCavwKI96Hl4irY96Tpos61Yues9oNihCWdbwTHKN0JNlz 0yVv7VctSl9nlUx28UQo7f1DqKFwO5To3jde6003FmSQkWNRwsN4BCxD8Lrkoo51ZKMj cY9Q== X-Gm-Message-State: ALoCoQlUixqWmP4jSO0imWUnQiSIjJFOy5c32cgqm0nbO1YHsDIcqImvK0TLXIU832S/yUSuIn8R X-Received: by 10.58.18.204 with SMTP id y12mr55043ved.36.1384686267135; Sun, 17 Nov 2013 03:04:27 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.2.69 with SMTP id 5ls979715qes.98.gmail; Sun, 17 Nov 2013 03:04:27 -0800 (PST) X-Received: by 10.52.103.35 with SMTP id ft3mr8339139vdb.5.1384686267041; Sun, 17 Nov 2013 03:04:27 -0800 (PST) Received: from mail-vc0-f173.google.com (mail-vc0-f173.google.com [209.85.220.173]) by mx.google.com with ESMTPS id lu1si5566626vcb.88.2013.11.17.03.04.27 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 17 Nov 2013 03:04:27 -0800 (PST) Received-SPF: neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.173; Received: by mail-vc0-f173.google.com with SMTP id lh4so2878566vcb.18 for ; Sun, 17 Nov 2013 03:04:27 -0800 (PST) X-Received: by 10.52.187.138 with SMTP id fs10mr8036246vdc.10.1384686266677; Sun, 17 Nov 2013 03:04:26 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp140355vcz; Sun, 17 Nov 2013 03:04:25 -0800 (PST) X-Received: by 10.194.250.6 with SMTP id yy6mr12912251wjc.13.1384686265289; Sun, 17 Nov 2013 03:04:25 -0800 (PST) Received: from mail-wi0-f181.google.com (mail-wi0-f181.google.com [209.85.212.181]) by mx.google.com with ESMTPS id jb15si2259826wic.51.2013.11.17.03.04.24 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 17 Nov 2013 03:04:25 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.181 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=209.85.212.181; Received: by mail-wi0-f181.google.com with SMTP id f4so2697481wiw.2 for ; Sun, 17 Nov 2013 03:04:24 -0800 (PST) X-Received: by 10.180.198.5 with SMTP id iy5mr13011923wic.45.1384686264628; Sun, 17 Nov 2013 03:04:24 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id fu1sm13156973wib.8.2013.11.17.03.04.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 17 Nov 2013 03:04:23 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Lee Jones Cc: devicetree@vger.kernel.org, Linus Walleij , Patrice Chotard Subject: [PATCH 01/21] ARM: ux500: move UART pin control to the device tree Date: Sun, 17 Nov 2013 12:03:50 +0100 Message-Id: <1384686250-10542-2-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1384686250-10542-1-git-send-email-linus.walleij@linaro.org> References: <1384686250-10542-1-git-send-email-linus.walleij@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This moves the static, device-tied pin control configuration out of the board file board-mop500-pins.c and into the device tree. We create a new .dtsi-file to be shared between all the MOP500-related boards, that include all HREF variants and the Snowball board. Assign pin states for HREF and Snowball boards alike. Cc: Lee Jones Cc: Patrice Chotard Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 114 +++++++++++++++++++++++++ arch/arm/boot/dts/ste-href.dtsi | 10 +++ arch/arm/boot/dts/ste-snowball.dts | 10 +++ arch/arm/mach-ux500/board-mop500-pins.c | 52 ----------- 4 files changed, 134 insertions(+), 52 deletions(-) create mode 100644 arch/arm/boot/dts/ste-href-family-pinctrl.dtsi diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi new file mode 100644 index 000000000000..d979de27b6e1 --- /dev/null +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -0,0 +1,114 @@ +/* + * Copyright 2013 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "ste-nomadik-pinctrl.dtsi" + +/ { + soc { + pinctrl { + /* Settings for all UART default and sleep states */ + uart0 { + uart0_default_mode: uart0_default { + default_mux { + ste,function = "u0"; + ste,pins = "u0_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ + ste,config = <&out_hi>; + }; + }; + + uart0_sleep_mode: uart0_sleep { + sleep_cfg1 { + ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + + sleep_cfg2 { + ste,pins = "GPIO1_AJ3"; /* RTS */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + + sleep_cfg3 { + ste,pins = "GPIO3_AH3"; /* TXD */ + ste,config = <&slpm_out_wkup_pdis>; + }; + }; + }; + + uart1 { + uart1_default_mode: uart1_default { + default_mux { + ste,function = "u1"; + ste,pins = "u1rxtx_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO4_AH6"; /* RXD */ + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO5_AG6"; /* TXD */ + ste,config = <&out_hi>; + }; + }; + + uart1_sleep_mode: uart1_sleep { + sleep_cfg1 { + ste,pins = "GPIO4_AH6"; /* RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + + sleep_cfg2 { + ste,pins = "GPIO5_AG6"; /* TXD */ + ste,config = <&slpm_out_wkup_pdis>; + }; + }; + }; + + uart2 { + uart2_default_mode: uart2_default { + default_mux { + ste,function = "u2"; + ste,pins = "u2rxtx_c_1"; + }; + default_cfg1 { + ste,pins = "GPIO29_W2"; /* RXD */ + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO30_W3"; /* TXD */ + ste,config = <&out_hi>; + }; + }; + + uart2_sleep_mode: uart2_sleep { + sleep_cfg1 { + ste,pins = "GPIO29_W2"; /* RXD */ + ste,config = <&in_wkup_pdis>; + }; + + sleep_cfg2 { + ste,pins = "GPIO30_W3"; /* TXD */ + ste,config = <&out_wkup_pdis>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index aa3f02060fdd..914a5f4399e5 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -11,6 +11,7 @@ #include #include "ste-dbx5x0.dtsi" +#include "ste-href-family-pinctrl.dtsi" / { memory { @@ -30,14 +31,23 @@ soc { uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; status = "okay"; }; uart@80121000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_default_mode>; + pinctrl-1 = <&uart1_sleep_mode>; status = "okay"; }; uart@80007000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_default_mode>; + pinctrl-1 = <&uart2_sleep_mode>; status = "okay"; }; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index f0b39f835914..16d28863ef6e 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "ste-dbx5x0.dtsi" +#include "ste-href-family-pinctrl.dtsi" / { model = "Calao Systems Snowball platform with device tree"; @@ -155,14 +156,23 @@ }; uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; status = "okay"; }; uart@80121000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_default_mode>; + pinctrl-1 = <&uart1_sleep_mode>; status = "okay"; }; uart@80007000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_default_mode>; + pinctrl-1 = <&uart2_sleep_mode>; status = "okay"; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0efb1560fc35..c6225191141f 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -65,16 +65,12 @@ BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); -BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| PIN_SLPM_PDIS_ENABLED); BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| PIN_SLPM_PDIS_DISABLED); -BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE| - PIN_SLPM_PDIS_DISABLED); /* We use these to define hog settings that are always done on boot */ #define DB8500_MUX_HOG(group,func) \ @@ -376,50 +372,10 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { */ DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu), /* - * UART0, we do not mux in u0 here. - * uart-0 pins gpio configuration should be kept intact to prevent - * a glitch in tx line when the tty dev is opened. Later these pins - * are configured by uart driver - */ - DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */ - DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */ - /* - * Mux in UART2 on altfunction C and set pull-ups. - * TODO: is this used on U8500 variants and Snowball really? - * The setting on GPIO31 conflicts with magnetometer use on hrefv60 - */ - /* default state for UART2 */ - DB8500_MUX("u2rxtx_c_1", "u2", "uart2"), - DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */ - DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */ - /* Sleep state for UART2 */ - DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"), - DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"), - /* * The following pin sets were known as "runtime pins" before being * converted to the pinctrl model. Here we model them as "default" * states. */ - /* Mux in UART0 after initialization */ - DB8500_MUX("u0_a_1", "u0", "uart0"), - DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */ - DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */ - DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */ - DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */ - /* Sleep state for UART0 */ - DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"), - /* Mux in UART1 after initialization */ - DB8500_MUX("u1rxtx_a_1", "u1", "uart1"), - DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */ - DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */ - /* Sleep state for UART1 */ - DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"), - DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"), /* MSP1 for ALSA codec */ DB8500_MUX_HOG("msp1txrx_a_1", "msp1"), DB8500_MUX_HOG("msp1_a_1", "msp1"), @@ -822,10 +778,6 @@ static struct pinctrl_map __initdata mop500_pinmap[] = { DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* TC35892 IRQ, pull up the line, let the driver mux in the pin */ DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu), - /* Mux in UART1 and set the pull-ups */ - DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */ /* * Runtime stuff: make it possible to mux in the SKE keypad * and bias the pins @@ -971,10 +923,6 @@ static struct pinctrl_map __initdata hrefv60_pinmap[] = { }; static struct pinctrl_map __initdata u9500_pinmap[] = { - /* Mux in UART1 (just RX/TX) and set the pull-ups */ - DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_PIN_HOG("GPIO4_AH6", in_pu), - DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* WLAN_IRQ line */ DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu), /* HSI */