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[128.107.239.234]) by mx.google.com with ESMTPSA id ry4sm36533776pab.4.2013.11.04.18.16.37 for (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128/128); Mon, 04 Nov 2013 18:16:38 -0800 (PST) From: Victor Kamensky To: linux-arm-kernel@lists.infradead.org, ben.dooks@codethink.co.uk, rmk@arm.linux.org.uk Cc: santosh.shilimkar@ti.com, r.sricharan@ti.com, nicolas.pitre@linaro.org, patches@linaro.org, linaro-kernel@lists.linaro.org, linaro-networking@linaro.org, Victor Kamensky Subject: [PATCH 3/3] ARM: fix mov to mvn conversion in case of 64 bit phys_addr_t and BE Date: Mon, 4 Nov 2013 18:16:05 -0800 Message-Id: <1383617765-28052-4-git-send-email-victor.kamensky@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1383617765-28052-1-git-send-email-victor.kamensky@linaro.org> References: <1383617765-28052-1-git-send-email-victor.kamensky@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: victor.kamensky@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.54 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Fix patching code to convert mov instruction into mvn instruction in case of CONFIG_ARCH_PHYS_ADDR_T_64BIT and CONFIG_ARM_PATCH_PHYS_VIRT. In BE case store into r0 proper bits so byte swapped instruction could be modified correctly. Signed-off-by: Victor Kamensky Reviewed-by: R Sricharan Acked-by: Santosh Shilimkar --- arch/arm/kernel/head.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index cd788d5..11d59b3 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -645,7 +645,11 @@ ARM_BE8(rev16 ip, ip) bcc 1b bx lr #else +#ifdef CONFIG_CPU_ENDIAN_BE8 + moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction +#else moveq r0, #0x400000 @ set bit 22, mov to mvn instruction +#endif b 2f 1: ldr ip, [r7, r3] #ifdef CONFIG_CPU_ENDIAN_BE8 @@ -654,7 +658,7 @@ ARM_BE8(rev16 ip, ip) tst ip, #0x000f0000 @ check the rotation field orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 biceq ip, ip, #0x00004000 @ clear bit 22 - orreq ip, ip, r0, lsl #24 @ mask in offset bits 7-0 + orreq ip, ip, r0 @ mask in offset bits 7-0 #else bic ip, ip, #0x000000ff tst ip, #0xf00 @ check the rotation field