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[188.246.204.87]) by mx.google.com with ESMTPSA id ey4sm8848624wic.11.2013.10.29.14.11.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Oct 2013 14:11:19 -0700 (PDT) From: Steve Capper To: linux-arm-kernel@lists.infradead.org Cc: will.deacon@arm.com, ard.biesheuvel@linaro.org, patches@linaro.org, Steve Capper Subject: [PATCH] arm64: Add hwcaps for crypto and CRC32 extensions. Date: Tue, 29 Oct 2013 21:10:38 +0000 Message-Id: <1383081038-3241-1-git-send-email-steve.capper@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: steve.capper@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.42 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Advertise the optional cryptographic and CRC32 instructions to user space where present. Several hwcap bits [2-6] are allocated. Signed-off-by: Steve Capper --- arch/arm64/include/uapi/asm/hwcap.h | 6 +++++- arch/arm64/kernel/setup.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index eea4975..2cd54ce 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -21,6 +21,10 @@ */ #define HWCAP_FP (1 << 0) #define HWCAP_ASIMD (1 << 1) - +#define HWCAP_AES (1 << 2) +#define HWCAP_PMULL (1 << 3) +#define HWCAP_SHA1 (1 << 4) +#define HWCAP_SHA2 (1 << 5) +#define HWCAP_CRC32 (1 << 6) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index add6ea6..d7a5f9c 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -100,6 +100,7 @@ void __init early_print(const char *str, ...) static void __init setup_processor(void) { struct cpu_info *cpu_info; + u64 features, block; /* * locate processor in the list of supported processor @@ -120,6 +121,37 @@ static void __init setup_processor(void) sprintf(init_utsname()->machine, "aarch64"); elf_hwcap = 0; + + /* + * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks. + * The blocks we test below represent incremental functionality + * for non-negative values. Negative values are reserved. + */ + features = read_cpuid(ID_AA64ISAR0_EL1); + block = (features >> 4) & 0xf; + if (!(block & 0x8)) { + switch (block) { + default: + case 2: + elf_hwcap |= HWCAP_PMULL; + case 1: + elf_hwcap |= HWCAP_AES; + case 0: + break; + } + } + + block = (features >> 8) & 0xf; + if (block && !(block & 0x8)) + elf_hwcap |= HWCAP_SHA1; + + block = (features >> 12) & 0xf; + if (block && !(block & 0x8)) + elf_hwcap |= HWCAP_SHA2; + + block = (features >> 16) & 0xf; + if (block && !(block & 0x8)) + elf_hwcap |= HWCAP_CRC32; } static void __init setup_machine_fdt(phys_addr_t dt_phys) @@ -309,6 +341,11 @@ subsys_initcall(topology_init); static const char *hwcap_str[] = { "fp", "asimd", + "aes", + "pmull", + "sha1", + "sha2", + "crc32", NULL };