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[24.6.79.41]) by mx.google.com with ESMTPSA id bp4sm85731419pbb.42.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 15 Oct 2013 21:50:56 -0700 (PDT) From: Victor Kamensky To: ben.dooks@codethink.co.uk, linux-arm-kernel@lists.infradead.org, nicolas.pitre@linaro.org, Dave.Martin@arm.com Cc: lorenzo.pieralisi@arm.com, will.deacon@arm.com, thomas.petazzoni@free-electrons.com, rmk@arm.linux.org.uk, patches@linaro.org, linaro-kernel@lists.linaro.org, Victor Kamensky Subject: [PATCH v2] ARM: cci driver need big endian fixes in asm code Date: Tue, 15 Oct 2013 21:50:34 -0700 Message-Id: <1381899034-420-2-git-send-email-victor.kamensky@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1381899034-420-1-git-send-email-victor.kamensky@linaro.org> References: <1381899034-420-1-git-send-email-victor.kamensky@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: victor.kamensky@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.53 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , cci_enable_port_for_self written in asm and it works with h/w registers that are in little endian format. When run in big endian mode it needs byteswaped constants before/after it writes/reads to/from such registers Signed-off-by: Victor Kamensky Signed-off-by: Ben Dooks Acked-by: Nicolas Pitre --- drivers/bus/arm-cci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 57b0bc6..4328c25 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -872,7 +872,7 @@ asmlinkage void __naked cci_enable_port_for_self(void) /* Enable the CCI port */ " ldr r0, [r0, %[offsetof_port_phys]] \n" -" mov r3, #"__stringify(CCI_ENABLE_REQ)" \n" +" mov r3, %[cci_enable_req]\n" " str r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n" /* poll the status reg for completion */ @@ -880,7 +880,7 @@ asmlinkage void __naked cci_enable_port_for_self(void) " ldr r0, [r1] \n" " ldr r0, [r0, r1] @ cci_ctrl_base \n" "4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n" -" tst r1, #1 \n" +" tst r1, %[cci_control_status_bits] \n" " bne 4b \n" " mov r0, #0 \n" @@ -893,6 +893,8 @@ asmlinkage void __naked cci_enable_port_for_self(void) "7: .word cci_ctrl_phys - . \n" : : [sizeof_cpu_port] "i" (sizeof(cpu_port)), + [cci_enable_req] "i" cpu_to_le32(CCI_ENABLE_REQ), + [cci_control_status_bits] "i" cpu_to_le32(1), #ifndef __ARMEB__ [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)), #else