From patchwork Mon Oct 7 12:12:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 20853 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ye0-f200.google.com (mail-ye0-f200.google.com [209.85.213.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E824024697 for ; Mon, 7 Oct 2013 12:14:11 +0000 (UTC) Received: by mail-ye0-f200.google.com with SMTP id r1sf7199969yen.11 for ; Mon, 07 Oct 2013 05:14:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=6fV76pYbP7TWw3/l84CNzH9wWnz6UxM8DVgQZEMWLvs=; b=UOn8bgeJSW/CmipcxrMYy4Yu02eKrBMcOqF6NwueN+8BUz8k1jTaTAKkHpAtQ3wSOE t56C1fWr3ECtjyQbcL+PSAYith7yhq/4RKV43pTC5txpVuhVJG1qfZHwJZnGhObWowRi gJwZL62aMdnuNJXeTWzzKiZq98PUcxzs8mDB40QHhv85Hc8OZxfiaUFdgc7jTyD09B36 ymWdG4PGmZMmVgaIAXQmpKP1QIgS1sQS0yha13K7JYCeqpydPkmvWFP1/aQ/D7wykzbW EdXyhwQ4YPN5E2XzaUw4gA94tNXflsTaNmR5uQqT6lJNvpV1Vay0Xw7YOO5V4C/rfVuh heYw== X-Received: by 10.236.223.130 with SMTP id v2mr25592405yhp.34.1381148051702; Mon, 07 Oct 2013 05:14:11 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.84.201 with SMTP id b9ls2402693qez.62.gmail; Mon, 07 Oct 2013 05:14:11 -0700 (PDT) X-Received: by 10.58.44.37 with SMTP id b5mr26284577vem.4.1381148051604; Mon, 07 Oct 2013 05:14:11 -0700 (PDT) Received: from mail-vc0-f175.google.com (mail-vc0-f175.google.com [209.85.220.175]) by mx.google.com with ESMTPS id wp10si7691469vdb.149.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 07 Oct 2013 05:14:11 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.175; Received: by mail-vc0-f175.google.com with SMTP id ia10so2769982vcb.20 for ; Mon, 07 Oct 2013 05:14:11 -0700 (PDT) X-Gm-Message-State: ALoCoQl6SqPbYhemyPkCixeHxD9a+FU2nZ/3iKiUQFI4UDpdwpaQ6LoLKAqK2yk4fuuWqQiOFihz X-Received: by 10.221.40.10 with SMTP id to10mr335359vcb.22.1381148051493; Mon, 07 Oct 2013 05:14:11 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp120355vcz; Mon, 7 Oct 2013 05:14:10 -0700 (PDT) X-Received: by 10.180.76.48 with SMTP id h16mr18573452wiw.32.1381148049839; Mon, 07 Oct 2013 05:14:09 -0700 (PDT) Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by mx.google.com with ESMTPS id n5si3956596wix.52.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 07 Oct 2013 05:14:09 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.43 is neither permitted nor denied by best guess record for domain of ard.biesheuvel@linaro.org) client-ip=74.125.82.43; Received: by mail-wg0-f43.google.com with SMTP id z12so6895942wgg.34 for ; Mon, 07 Oct 2013 05:14:09 -0700 (PDT) X-Received: by 10.180.187.51 with SMTP id fp19mr18692370wic.1.1381148049297; Mon, 07 Oct 2013 05:14:09 -0700 (PDT) Received: from ards-mac-mini.local ([83.153.85.71]) by mx.google.com with ESMTPSA id ma3sm38759714wic.1.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 07 Oct 2013 05:14:08 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, nico@linaro.org, patches@linaro.org, Ard Biesheuvel Subject: [RFC PATCH 1/5] ARM64: allow limited use of some NEON registers in exceptions Date: Mon, 7 Oct 2013 14:12:27 +0200 Message-Id: <1381147951-7609-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1381147951-7609-1-git-send-email-ard.biesheuvel@linaro.org> References: <1381147951-7609-1-git-send-email-ard.biesheuvel@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Stack/unstack the bottom 4 NEON registers on exception entry/exit so we can use them in places where we are not allowed to sleep. Signed-off-by: Ard Biesheuvel --- arch/arm64/Kconfig | 14 ++++++++++++++ arch/arm64/include/asm/ptrace.h | 3 +++ arch/arm64/kernel/asm-offsets.c | 3 +++ arch/arm64/kernel/entry.S | 8 ++++++++ 4 files changed, 28 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c044548..b97a458 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -98,6 +98,9 @@ config IOMMU_HELPER config KERNEL_MODE_NEON def_bool y +config STACK_NEON_REGS_ON_EXCEPTION + def_bool n + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -219,6 +222,17 @@ config FORCE_MAX_ZONEORDER default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) default "11" +config KERNEL_MODE_SYNC_CE_CRYPTO + bool "Support for synchronous crypto ciphers using Crypto Extensions" + depends on KERNEL_MODE_NEON + select STACK_NEON_REGS_ON_EXCEPTION + help + This enables support for using ARMv8 Crypto Extensions instructions + in places where sleeping is not allowed. The synchronous ciphers are + only allowed to use the bottom 4 NEON register q0 - q3, as stacking + the entire NEON register file at every exception is too costly. + + endmenu menu "Boot options" diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 0dacbbf..17ea483 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -103,6 +103,9 @@ struct pt_regs { }; u64 orig_x0; u64 syscallno; +#ifdef CONFIG_STACK_NEON_REGS_ON_EXCEPTION + struct { u64 l, h; } qregs[4]; +#endif }; #define arch_has_single_step() (1) diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index 666e231..73c944a 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -58,6 +58,9 @@ int main(void) DEFINE(S_PC, offsetof(struct pt_regs, pc)); DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0)); DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno)); +#ifdef CONFIG_STACK_NEON_REGS_ON_EXCEPTION + DEFINE(S_QREGS, offsetof(struct pt_regs, qregs)); +#endif DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); BLANK(); DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 3881fd1..c74dcca 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -58,6 +58,10 @@ push x4, x5 push x2, x3 push x0, x1 +#ifdef CONFIG_STACK_NEON_REGS_ON_EXCEPTION + add x21, sp, #S_QREGS + st1 {v0.16b-v3.16b}, [x21] +#endif .if \el == 0 mrs x21, sp_el0 .else @@ -86,6 +90,10 @@ .endm .macro kernel_exit, el, ret = 0 +#ifdef CONFIG_STACK_NEON_REGS_ON_EXCEPTION + add x21, sp, #S_QREGS + ld1 {v0.16b-v3.16b}, [x21] +#endif ldp x21, x22, [sp, #S_PC] // load ELR, SPSR .if \el == 0 ldr x23, [sp, #S_SP] // load return stack pointer