From patchwork Mon Oct 7 10:27:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taras Kondratiuk X-Patchwork-Id: 20851 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f199.google.com (mail-ve0-f199.google.com [209.85.128.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5EE2124697 for ; Mon, 7 Oct 2013 10:27:14 +0000 (UTC) Received: by mail-ve0-f199.google.com with SMTP id db12sf15443683veb.10 for ; Mon, 07 Oct 2013 03:27:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=DVR+auhsMZWKjWa2xB4TQ2AW0QB4rJ2D9EXnCY8FECA=; b=V8BcxBBn9MKOzJ+tKIfn8sRx2GASFs2N1NpI9spYMYUedt1/0eJvBqzjoWKW3U3Kob mtvwSQJsH71ONXhlAvHy++VuYCZ+2Dspz9oSAI7dAeyGCq4olhXOXKQn5mH4pYBseRAu gsXKEfXA0uoORmjT6vWcFkfJjVuAotrUqiUJaKpo9Bu5j887pQwAC25xQYv6anflDWWA Rbi8mRQriigDmDLcEw4gV1azj6dBBxzh2ysmh1lrC13KMyM0rW61nhEn3lbUg2klvpmS IAnGwhC5LvK4WVoRzrj9R80lO+1K475NlcYImBEvu6IJSzA4W/BBrzzjn6fKdDikvgPH bM8A== X-Received: by 10.236.101.103 with SMTP id a67mr24686575yhg.25.1381141633756; Mon, 07 Oct 2013 03:27:13 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.29.6 with SMTP id f6ls693894qeh.3.gmail; Mon, 07 Oct 2013 03:27:13 -0700 (PDT) X-Received: by 10.52.65.136 with SMTP id x8mr917142vds.23.1381141633665; Mon, 07 Oct 2013 03:27:13 -0700 (PDT) Received: from mail-vc0-f175.google.com (mail-vc0-f175.google.com [209.85.220.175]) by mx.google.com with ESMTPS id de6si7619280vcb.109.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 07 Oct 2013 03:27:13 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.175; Received: by mail-vc0-f175.google.com with SMTP id ia10so2720536vcb.6 for ; Mon, 07 Oct 2013 03:27:13 -0700 (PDT) X-Gm-Message-State: ALoCoQmLMe1RGb6sVQLqnxF2jpRSb9Yg6qq1otwpYmp/DrQTuANZH+UEWbBYbO3BIUpXqujycSnp X-Received: by 10.58.46.229 with SMTP id y5mr26057439vem.15.1381141633558; Mon, 07 Oct 2013 03:27:13 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp114018vcz; Mon, 7 Oct 2013 03:27:13 -0700 (PDT) X-Received: by 10.14.178.67 with SMTP id e43mr1969455eem.59.1381141632514; Mon, 07 Oct 2013 03:27:12 -0700 (PDT) Received: from mail-ea0-f181.google.com (mail-ea0-f181.google.com [209.85.215.181]) by mx.google.com with ESMTPS id q8si22569069eem.60.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 07 Oct 2013 03:27:12 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.215.181 is neither permitted nor denied by best guess record for domain of taras.kondratiuk@linaro.org) client-ip=209.85.215.181; Received: by mail-ea0-f181.google.com with SMTP id d10so3069045eaj.26 for ; Mon, 07 Oct 2013 03:27:11 -0700 (PDT) X-Received: by 10.15.67.131 with SMTP id u3mr47714106eex.34.1381141631281; Mon, 07 Oct 2013 03:27:11 -0700 (PDT) Received: from condor-x220.synapse.com ([195.238.93.36]) by mx.google.com with ESMTPSA id v8sm61665308eeo.12.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 07 Oct 2013 03:27:10 -0700 (PDT) From: Taras Kondratiuk To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, steve.mcintyre@linaro.org, Will Deacon , Russell King , Rob Herring , Santosh Shilimkar , linaro-kernel@lists.linaro.org, linux-omap@vger.kernel.org Subject: [PATCH] ARM: OMAP4/highbank: Flush L2 cache before disabling Date: Mon, 7 Oct 2013 13:27:01 +0300 Message-Id: <1381141621-29001-1-git-send-email-taras.kondratiuk@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: taras.kondratiuk@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Kexec disables outer cache before jumping to reboot code, but it doesn't flush it explicitly. Flush is done implicitly inside of l2x0_disable(). But some SoC's override default .disable handler and don't flush cache. This may lead to a corrupted memory during Kexec reboot on these platforms. This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable() handlers to make it consistent with default l2x0_disable(). Also it removes redundant outer_flush_all() call just before outer_disable(). Acked-by: Rob Herring Acked-by: Santosh Shilimkar Signed-off-by: Taras Kondratiuk Acked-by: Tony Lindgren --- Based on v3.12-rc3 RFC v2: https://patchwork.kernel.org/patch/2990231/ Make the fix specific to platforms that don't use l2x0_disable(). RFC v1: https://patchwork.kernel.org/patch/2974431/ --- Cc: Will Deacon Cc: Russell King Cc: Rob Herring Cc: Santosh Shilimkar Cc: linaro-kernel@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org --- arch/arm/mach-highbank/highbank.c | 1 + arch/arm/mach-highbank/pm.c | 1 - arch/arm/mach-omap2/omap4-common.c | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index 8e63ccd..22e6f34 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -63,6 +63,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr) static void highbank_l2x0_disable(void) { + outer_flush_all(); /* Disable PL310 L2 Cache controller */ highbank_smc1(0x102, 0x0); } diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c index 04eddb4..9a5b8a7 100644 --- a/arch/arm/mach-highbank/pm.c +++ b/arch/arm/mach-highbank/pm.c @@ -28,7 +28,6 @@ static int highbank_suspend_finish(unsigned long val) { - outer_flush_all(); outer_disable(); highbank_set_pwr_suspend(); diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 2840d1e..f6ccab61 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -163,6 +163,7 @@ void __iomem *omap4_get_l2cache_base(void) static void omap4_l2x0_disable(void) { + outer_flush_all(); /* Disable PL310 L2 Cache controller */ omap_smc1(0x102, 0x0); }