From patchwork Mon Oct 7 06:47:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vkamensky X-Patchwork-Id: 20844 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f71.google.com (mail-yh0-f71.google.com [209.85.213.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 870CD25DFC for ; Mon, 7 Oct 2013 06:48:38 +0000 (UTC) Received: by mail-yh0-f71.google.com with SMTP id f73sf12874491yha.10 for ; Sun, 06 Oct 2013 23:48:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=6qtfn3WY0OAj+BKOSpK3WYXNg5XAF7CRms57NMEX+yA=; b=FPzMjkqUto1qR8b6xpeamjC0RaIjbNhUbv5qRDfGgtuzdq092/W0LyrVxmVuU8NCVn dFtch4W64H35Yh9i1ODAi5gIFRQ8SVmFaOnJostCsPkWKMF6JKLUz7CEcNRcH7FK1WpQ EcdBt8hWx5RedS2Z8d6GVTu/i27cPOTPZY+gBh5HK5dV/R03eFf6YqwBUW3l/DTW1URq exm0e016pZEnpZdjSR+b42sHlreQWuyntQpga7we1T13+R44DrbdXvBYIvrWZdUheYcs NKxQeQ1JUxs4sX2mSEI8DNYKqh6QGvFrTUgGgKl7+tFBnqOR3iJtd1duoLllwxxVVZC5 gRCA== X-Received: by 10.236.147.18 with SMTP id s18mr28597498yhj.28.1381128518334; Sun, 06 Oct 2013 23:48:38 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.35.244 with SMTP id l20ls2350151qej.98.gmail; Sun, 06 Oct 2013 23:48:38 -0700 (PDT) X-Received: by 10.59.9.138 with SMTP id ds10mr25204944ved.5.1381128518166; Sun, 06 Oct 2013 23:48:38 -0700 (PDT) Received: from mail-ve0-f179.google.com (mail-ve0-f179.google.com [209.85.128.179]) by mx.google.com with ESMTPS id c8si7428279vcq.63.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 06 Oct 2013 23:48:38 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.179; Received: by mail-ve0-f179.google.com with SMTP id c14so3445243vea.38 for ; Sun, 06 Oct 2013 23:48:38 -0700 (PDT) X-Gm-Message-State: ALoCoQl4TibZ24Xbmi1rILZjpkjcZ1GUBpCBHl/28dJ4AT1eo/P2GdMrkui9lpseudpuDZ6kUXHc X-Received: by 10.58.46.229 with SMTP id y5mr25304004vem.15.1381128518065; Sun, 06 Oct 2013 23:48:38 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp102374vcz; Sun, 6 Oct 2013 23:48:37 -0700 (PDT) X-Received: by 10.68.225.42 with SMTP id rh10mr1221516pbc.176.1381128517177; Sun, 06 Oct 2013 23:48:37 -0700 (PDT) Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by mx.google.com with ESMTPS id qc9si21416728pac.8.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 06 Oct 2013 23:48:37 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.46 is neither permitted nor denied by best guess record for domain of victor.kamensky@linaro.org) client-ip=209.85.220.46; Received: by mail-pa0-f46.google.com with SMTP id fa1so6851867pad.19 for ; Sun, 06 Oct 2013 23:48:36 -0700 (PDT) X-Received: by 10.68.34.197 with SMTP id b5mr163670pbj.188.1381128513661; Sun, 06 Oct 2013 23:48:33 -0700 (PDT) Received: from kamensky-w530.cisco.com.com (128-107-239-233.cisco.com. [128.107.239.233]) by mx.google.com with ESMTPSA id xv2sm31048683pbb.39.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 06 Oct 2013 23:48:33 -0700 (PDT) From: Victor Kamensky To: will.deacon@arm.com, linux-arm-kernel@lists.infradead.org Cc: ben.dooks@codethink.co.uk, steve.mcintyre@linaro.org, patches@linaro.org, linaro-kernel@lists.linaro.org, linaro-networking@linaro.org, Victor Kamensky Subject: [PATCH] ARM: tlb: __flush_tlb_mm need to use int asid var for BE correct operation Date: Sun, 6 Oct 2013 23:47:38 -0700 Message-Id: <1381128458-32140-2-git-send-email-victor.kamensky@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1381128458-32140-1-git-send-email-victor.kamensky@linaro.org> References: <1381128458-32140-1-git-send-email-victor.kamensky@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: victor.kamensky@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.179 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , __flush_tlb_mm function need to use intermediate 'int' type 'asid' variable int tlb_op macro call. Direct use of ASID macro produces 64 bit unsigned long long type passed to inline assembler statement as 'r' operand (32bit), and resulting behavior is not well specified. It works in little endian case, but is broken in big endian case. In big endian case gcc generate such code that 0 is passed to 'mcr 15, 0, r4, cr8, cr3, {2}' operation. Note other functions like __local_flush_tlb_mm, and local_flush_tlb_mm already use intermediate 'asid' variable in similar code. Signed-off-by: Victor Kamensky --- arch/arm/include/asm/tlbflush.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 3896026..b4d70ad 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -399,6 +399,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) static inline void __flush_tlb_mm(struct mm_struct *mm) { + const int asid = ASID(mm); const unsigned int __tlb_flag = __cpu_tlb_flags; if (tlb_flag(TLB_WB)) @@ -408,7 +409,7 @@ static inline void __flush_tlb_mm(struct mm_struct *mm) #ifdef CONFIG_ARM_ERRATA_720789 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", 0); #else - tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", ASID(mm)); + tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid); #endif if (tlb_flag(TLB_BARRIER))