From patchwork Tue Sep 3 09:29:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 19702 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f198.google.com (mail-vc0-f198.google.com [209.85.220.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id DBD0E24869 for ; Tue, 3 Sep 2013 09:30:14 +0000 (UTC) Received: by mail-vc0-f198.google.com with SMTP id ht10sf6170108vcb.9 for ; Tue, 03 Sep 2013 02:30:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=IZluyq4ybtqtzSarOHxRcGHA/dtzY5CrX6js7960b/Q=; b=fkgFr3raBQzy9CLHyrRYvub65mB2VVT4Sh/9yMpjqu0V14VhbW48/mH5DjKhMqFoAg +ljvxetxOmWXqmKyxcwfcmv/GHmrH26V1zPZVbrb6uqNT/wbkJYlm5f55kVodDw+kbRW Gim8/wQ9rpu2nGACU6jzmb/7S33eZqKLGezjg3BYoiQwYFAAbJdElWyEczshbn32k6oW ByzoO1h6pLKxTS4BJZ25XdXy4Z2l7b05m3iHpo3UQ+klvHs2T/uZOYizD5VdOm3KZoro w1GTk2VxGqbE5SOSrS5e3JE1bffWGtM0PhI/NyRSzYW5jMQo7QoqjzqHY/KZXnl87j90 2b6A== X-Received: by 10.236.32.74 with SMTP id n50mr10044678yha.13.1378200614613; Tue, 03 Sep 2013 02:30:14 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.50.225 with SMTP id f1ls2403179qeo.66.gmail; Tue, 03 Sep 2013 02:30:14 -0700 (PDT) X-Received: by 10.58.75.41 with SMTP id z9mr27739677vev.4.1378200614522; Tue, 03 Sep 2013 02:30:14 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id x9si4179899vec.118.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Sep 2013 02:30:14 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id gd11so3717729vcb.33 for ; Tue, 03 Sep 2013 02:30:14 -0700 (PDT) X-Gm-Message-State: ALoCoQnLOslx0ye98+IrD9mPkFyebAJTPCFnTmuaE5e4hQWG4bjbakw5h52X7CHzOEfjVkzcTCpw X-Received: by 10.58.196.132 with SMTP id im4mr21807vec.28.1378200614417; Tue, 03 Sep 2013 02:30:14 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp160149vcz; Tue, 3 Sep 2013 02:30:13 -0700 (PDT) X-Received: by 10.15.101.73 with SMTP id bo49mr613505eeb.82.1378200613218; Tue, 03 Sep 2013 02:30:13 -0700 (PDT) Received: from mail-ee0-f44.google.com (mail-ee0-f44.google.com [74.125.83.44]) by mx.google.com with ESMTPS id h46si12536137eex.253.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Sep 2013 02:30:13 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.83.44 is neither permitted nor denied by best guess record for domain of ulf.hansson@linaro.org) client-ip=74.125.83.44; Received: by mail-ee0-f44.google.com with SMTP id b47so2874064eek.31 for ; Tue, 03 Sep 2013 02:30:12 -0700 (PDT) X-Received: by 10.14.246.11 with SMTP id p11mr45496537eer.9.1378200612688; Tue, 03 Sep 2013 02:30:12 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id z12sm29882771eev.6.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Sep 2013 02:30:12 -0700 (PDT) From: Ulf Hansson To: linux-arm-kernel@lists.infradead.org, Russell King Cc: linux-mmc@vger.kernel.org, Chris Ball , Daniel Lezcano , Linus Walleij , Ulf Hansson , Johan Rudholm Subject: [PATCH V3 3/4] mmc: mmci: Adapt to register write restrictions Date: Tue, 3 Sep 2013 11:29:35 +0200 Message-Id: <1378200576-13413-4-git-send-email-ulf.hansson@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1378200576-13413-1-git-send-email-ulf.hansson@linaro.org> References: <1378200576-13413-1-git-send-email-ulf.hansson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ulf.hansson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , After a write to the MMCICLOCK register data cannot be written to this register for three feedback clock cycles. Writes to the MMCIPOWER register must be separated by three MCLK cycles. Previously no issues has been observered, but using higher ARM clock frequencies on STE- platforms has triggered this problem. The MMCICLOCK register is written to in .set_ios and for some data transmissions for SDIO. We do not need a delay at the data transmission path, because sending and receiving data will require more than three clock cycles. Then we use a simple logic to only delay in .set_ios and thus we don't affect throughput performance. Signed-off-by: Johan Rudholm Signed-off-by: Ulf Hansson Acked-by: Rickard Andersson --- drivers/mmc/host/mmci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index c550b3e..82afcd3 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -189,6 +189,21 @@ static int mmci_validate_data(struct mmci_host *host, return 0; } +static void mmci_reg_delay(struct mmci_host *host) +{ + /* + * According to the spec, at least three feedback clock cycles + * of max 52 MHz must pass between two writes to the MMCICLOCK reg. + * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. + * Worst delay time during card init is at 100 kHz => 30 us. + * Worst delay time when up and running is at 25 MHz => 120 ns. + */ + if (host->cclk < 20000000) + udelay(30); + else + ndelay(120); +} + /* * This must be called with host->lock held */ @@ -1264,6 +1279,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) mmci_set_clkreg(host, ios->clock); mmci_write_pwrreg(host, pwr); + mmci_reg_delay(host); spin_unlock_irqrestore(&host->lock, flags);