From patchwork Tue Aug 6 04:41:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 18785 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ve0-f200.google.com (mail-ve0-f200.google.com [209.85.128.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B19F42486D for ; Tue, 6 Aug 2013 04:41:39 +0000 (UTC) Received: by mail-ve0-f200.google.com with SMTP id oz10sf5747382veb.3 for ; Mon, 05 Aug 2013 21:41:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state:x-removed-original-auth:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=sgvBeZmzC0Ib6zx0H841A28S7Vf+l8DZQa8TrqaaksU=; b=BZXqk1GunLajZ+c24kja2gkwUET2ubOFUJd//fmTXn5/TJmjbfyBMtmPgmHL0e8Cqo oY3Ef748WwPoiPf7aNa/WuwMzc8/cx4O+eXtyYsnAumvHRjz65tEsn+jA3Fy9GQ6WDwb m8hs6s8bTi6psdREL1hhZC3A+joJBlc3cJGE52TKodD1Ddvz4poeY8wKCkgxlqFmCHr7 Ze8uRsZvZSWHQ2SH9c3agHYrCLQxhCG/gSpVURpRv+nKpDcgnBIkUtzOD6pVqfqBjxqC p2RcdkFkCCAtDwKwJRGb1axvAxFjQn1lafMRv1rVd4POUaRa0somZP4cp96JkcoYl9pX Aohg== X-Received: by 10.236.112.33 with SMTP id x21mr9335343yhg.57.1375764099330; Mon, 05 Aug 2013 21:41:39 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.1.227 with SMTP id 3ls59843qep.5.gmail; Mon, 05 Aug 2013 21:41:39 -0700 (PDT) X-Received: by 10.52.161.33 with SMTP id xp1mr5791566vdb.55.1375764099166; Mon, 05 Aug 2013 21:41:39 -0700 (PDT) Received: from mail-vb0-f45.google.com (mail-vb0-f45.google.com [209.85.212.45]) by mx.google.com with ESMTPS id jf10si544170vdb.115.2013.08.05.21.41.39 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 05 Aug 2013 21:41:39 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.45 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.45; Received: by mail-vb0-f45.google.com with SMTP id e15so3684630vbg.32 for ; Mon, 05 Aug 2013 21:41:39 -0700 (PDT) X-Received: by 10.58.154.34 with SMTP id vl2mr6937508veb.35.1375764098981; Mon, 05 Aug 2013 21:41:38 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.11.8 with SMTP id pc8csp126773vcb; Mon, 5 Aug 2013 21:41:38 -0700 (PDT) X-Received: by 10.66.232.167 with SMTP id tp7mr1091734pac.15.1375764097844; Mon, 05 Aug 2013 21:41:37 -0700 (PDT) Received: from mail-pd0-x22a.google.com (mail-pd0-x22a.google.com [2607:f8b0:400e:c02::22a]) by mx.google.com with ESMTPS id km7si1509811pbc.185.2013.08.05.21.41.37 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 05 Aug 2013 21:41:37 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400e:c02::22a is neither permitted nor denied by best guess record for domain of christoffer.dall@linaro.org) client-ip=2607:f8b0:400e:c02::22a; Received: by mail-pd0-f170.google.com with SMTP id x10so4097061pdj.1 for ; Mon, 05 Aug 2013 21:41:37 -0700 (PDT) X-Received: by 10.68.189.103 with SMTP id gh7mr25602220pbc.142.1375764097156; Mon, 05 Aug 2013 21:41:37 -0700 (PDT) Received: from localhost.localdomain (c-67-169-183-77.hsd1.ca.comcast.net. [67.169.183.77]) by mx.google.com with ESMTPSA id 4sm2636673pbw.32.2013.08.05.21.41.35 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 05 Aug 2013 21:41:36 -0700 (PDT) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linaro-kernel@lists.linaro.org, patches@linaro.org, Christoffer Dall Subject: [PATCH] ARM: KVM: Fix 64-bit coprocessor handling Date: Mon, 5 Aug 2013 21:41:26 -0700 Message-Id: <1375764086-1996-1-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQkxgIM8LpwFJZpQEmMXOhKfiGcrze6klwwI/6hZZHoFWFboTKCtsiSHYYdouwYuEvGp6TOW X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: christoffer.dall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.45 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The PAR was exported as CRn == 7 and CRm == 0, but in fact the primary coprocessor register number was determined by CRm for 64-bit coprocessor registers as the user space API was modelled after the coprocessor access instructions (see the ARM ARM rev. C - B3-1445). However, just changing the CRn to CRm breaks the sorting check when booting the kernel, because the internal kernel logic always treats CRn as the primary register number, and it makes the table sorting impossible to understand for humans. Alternatively we could change the logic to always have CRn == CRm, but that becomes unclear in the number of ways we do lookup of a coprocessor register. We could also have a separate 64-bit table but that feels somewhat over-engineerd. Instead, keep CRn the primary representation of the primary corproc. register number in-kernel and always export the primary number as CRm as per the existing user space ABI. Note: The TTBR registers just magically worked because they happened to follow the CRn(0) regs and were considered CRn(0) in the in-kernel representation. Signed-off-by: Christoffer Dall --- arch/arm/kvm/coproc.c | 23 +++++++++++++++++------ arch/arm/kvm/coproc.h | 2 ++ arch/arm/kvm/coproc_a15.c | 5 ++++- 3 files changed, 23 insertions(+), 7 deletions(-) diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index 4a51990..fc5fec2 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -146,7 +146,10 @@ static bool pm_fake(struct kvm_vcpu *vcpu, #define access_pmintenclr pm_fake /* Architected CP15 registers. - * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 + * CRn denotes the primary register number, but is copied to the CRm in the + * user space API in line with the terminology used in the ARM ARM. + * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit + * registers preceeding 32-bit ones. */ static const struct coproc_reg cp15_regs[] = { /* CSSELR: swapped by interrupt.S. */ @@ -154,8 +157,8 @@ static const struct coproc_reg cp15_regs[] = { NULL, reset_unknown, c0_CSSELR }, /* TTBR0/TTBR1: swapped by interrupt.S. */ - { CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 }, - { CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 }, + { CRn( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 }, + { CRn( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 }, /* TTBCR: swapped by interrupt.S. */ { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32, @@ -399,12 +402,13 @@ static bool index_to_params(u64 id, struct coproc_params *params) | KVM_REG_ARM_OPC1_MASK)) return false; params->is_64bit = true; - params->CRm = ((id & KVM_REG_ARM_CRM_MASK) + /* CRm to CRn: see cp15_to_index for details */ + params->CRn = ((id & KVM_REG_ARM_CRM_MASK) >> KVM_REG_ARM_CRM_SHIFT); params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK) >> KVM_REG_ARM_OPC1_SHIFT); params->Op2 = 0; - params->CRn = 0; + params->CRm = 0; return true; default: return false; @@ -898,7 +902,14 @@ static u64 cp15_to_index(const struct coproc_reg *reg) if (reg->is_64) { val |= KVM_REG_SIZE_U64; val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); - val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT); + /* + * CRn always denotes the primary coproc. reg. nr. for the + * in-kernel representation, but the user space API uses the + * CRm for the encoding, because it is modelled after the + * MRRC/MCRR instructions: see the ARM ARM rev. c page + * B3-1445 + */ + val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT); } else { val |= KVM_REG_SIZE_U32; val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); diff --git a/arch/arm/kvm/coproc.h b/arch/arm/kvm/coproc.h index b7301d3..dccb904 100644 --- a/arch/arm/kvm/coproc.h +++ b/arch/arm/kvm/coproc.h @@ -135,6 +135,8 @@ static inline int cmp_reg(const struct coproc_reg *i1, return -1; if (i1->CRn != i2->CRn) return i1->CRn - i2->CRn; + if (i1->is_64 != i2->is_64) + return i2->is_64 - i1->is_64; if (i1->CRm != i2->CRm) return i1->CRm - i2->CRm; if (i1->Op1 != i2->Op1) diff --git a/arch/arm/kvm/coproc_a15.c b/arch/arm/kvm/coproc_a15.c index 685063a..3d8f61f 100644 --- a/arch/arm/kvm/coproc_a15.c +++ b/arch/arm/kvm/coproc_a15.c @@ -114,7 +114,10 @@ static bool access_l2ectlr(struct kvm_vcpu *vcpu, /* * A15-specific CP15 registers. - * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 + * CRn denotes the primary register number, but is copied to the CRm in the + * user space API in line with the terminology used in the ARM ARM. + * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit + * registers preceeding 32-bit ones. */ static const struct coproc_reg a15_regs[] = { /* MPIDR: we use VMPIDR for guest access. */