From patchwork Tue Jul 23 03:31:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 18529 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-gh0-f199.google.com (mail-gh0-f199.google.com [209.85.160.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E7A592777E for ; Tue, 23 Jul 2013 03:31:51 +0000 (UTC) Received: by mail-gh0-f199.google.com with SMTP id g14sf8563017ghb.6 for ; Mon, 22 Jul 2013 20:31:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe :content-transfer-encoding; bh=wI1BV3F9Kbdjem2cWh02gdZ4oVF5Q6zUUOKOSnZMero=; b=ae9tvPwJvRBxmwL5C321nA3MOj+7+p+QZhw33UcHQgCBR0RfNbo5GkfDXSkloIbCyd gj2rqT2hi0Sn8rOtK1//o61IaeVnZLgy/MCWtyJxGBR3IsVbL8FZ/5nPMPyuweexhBU0 spwk01/wh/1y1nF7QslfqvevOoVNoHNKQs1zukUongFxXcoYqi4xP5H61GtezOIJIH5b 0FiWPiZK5B9VTeP+LksygPB634b2iFiu6zTLNMc+wRAWkn50fodSyfOtQpWnwdtqLdbp 2+j52O0QTNLxhfV+aYG+dQwYRoBqlpX1Dpal76ojE38hT8R8yUPpCQ8M38zPIpCI5yhH ZOqQ== X-Received: by 10.236.135.66 with SMTP id t42mr17743563yhi.36.1374550311458; Mon, 22 Jul 2013 20:31:51 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.48.49 with SMTP id i17ls3047090qen.45.gmail; Mon, 22 Jul 2013 20:31:51 -0700 (PDT) X-Received: by 10.52.72.169 with SMTP id e9mr8636073vdv.112.1374550311229; Mon, 22 Jul 2013 20:31:51 -0700 (PDT) Received: from mail-ve0-f181.google.com (mail-ve0-f181.google.com [209.85.128.181]) by mx.google.com with ESMTPS id tk7si7826804vdc.26.2013.07.22.20.31.51 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 22 Jul 2013 20:31:51 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.181; Received: by mail-ve0-f181.google.com with SMTP id db10so5558742veb.26 for ; Mon, 22 Jul 2013 20:31:51 -0700 (PDT) X-Received: by 10.52.77.5 with SMTP id o5mr8604545vdw.46.1374550311144; Mon, 22 Jul 2013 20:31:51 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.165.8 with SMTP id yu8csp84149veb; Mon, 22 Jul 2013 20:31:50 -0700 (PDT) X-Received: by 10.224.87.194 with SMTP id x2mr20903761qal.30.1374550306238; Mon, 22 Jul 2013 20:31:46 -0700 (PDT) Received: from relais.videotron.ca (relais.videotron.ca. [24.201.245.36]) by mx.google.com with ESMTP id b11si5234490qcv.81.2013.07.22.20.31.45 for ; Mon, 22 Jul 2013 20:31:46 -0700 (PDT) Received-SPF: neutral (google.com: 24.201.245.36 is neither permitted nor denied by best guess record for domain of nicolas.pitre@linaro.org) client-ip=24.201.245.36; Received: from yoda.home ([70.83.209.44]) by VL-VM-MR004.ip.videotron.ca (Oracle Communications Messaging Exchange Server 7u4-22.01 64bit (built Apr 21 2011)) with ESMTP id <0MQD009ECDSV4940@VL-VM-MR004.ip.videotron.ca>; Mon, 22 Jul 2013 23:31:44 -0400 (EDT) Received: from xanadu.home (xanadu.home [192.168.2.2]) by yoda.home (Postfix) with ESMTP id EA7052DA066D; Mon, 22 Jul 2013 23:31:43 -0400 (EDT) From: Nicolas Pitre To: linux-arm-kernel@lists.infradead.org Cc: dave.martin@linaro.org, lorenzo.pieralisi@arm.com, patches@linaro.org Subject: [PATCH 08/13] ARM: bL_switcher: do not hardcode GIC IDs in the code Date: Mon, 22 Jul 2013 23:31:24 -0400 Message-id: <1374550289-25305-9-git-send-email-nicolas.pitre@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-reply-to: <1374550289-25305-1-git-send-email-nicolas.pitre@linaro.org> References: <1374550289-25305-1-git-send-email-nicolas.pitre@linaro.org> X-Gm-Message-State: ALoCoQkedziJagxpsHuw3f8wk1zUbNdZF7sEso6HVfXa55gV/mPfkHOtH8Mnz6RNdcXId7a9Yn8V X-Original-Sender: nicolas.pitre@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Content-transfer-encoding: 7BIT Currently, GIC IDs are hardcoded making the code dependent on the 4+4 b.L configuration. Let's allow for GIC IDs to be discovered upon switcher initialization to support other b.L configurations such as the 1+1 one, or 2+3 as on the VExpress TC2. Signed-off-by: Nicolas Pitre --- arch/arm/common/bL_switcher.c | 14 +++++++++++++- drivers/irqchip/irq-gic.c | 21 +++++++++++++++++++++ include/linux/irqchip/arm-gic.h | 1 + 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm/common/bL_switcher.c b/arch/arm/common/bL_switcher.c index 4273be76ba..34eff3bc25 100644 --- a/arch/arm/common/bL_switcher.c +++ b/arch/arm/common/bL_switcher.c @@ -111,6 +111,8 @@ static int bL_switchpoint(unsigned long _arg) * Generic switcher interface */ +static unsigned int bL_gic_id[MAX_CPUS_PER_CLUSTER][MAX_NR_CLUSTERS]; + /* * bL_switch_to - Switch to a specific cluster for the current CPU * @new_cluster_id: the ID of the cluster to switch to. @@ -160,7 +162,7 @@ static int bL_switch_to(unsigned int new_cluster_id) this_cpu = smp_processor_id(); /* redirect GIC's SGIs to our counterpart */ - gic_migrate_target(cpuid + ib_cluster*4); + gic_migrate_target(bL_gic_id[cpuid][ib_cluster]); /* * Raise a SGI on the inbound CPU to make sure it doesn't stall @@ -338,6 +340,16 @@ static int __init bL_switcher_halve_cpus(void) cluster = (cpu_logical_map(i) >> 8) & 0xff; if (cpumask_test_cpu(cpu, &common_mask)) { + /* Let's take note of the GIC ID for this CPU */ + int gic_id = gic_get_cpu_id(i); + if (gic_id < 0) { + pr_err("%s: bad GIC ID for CPU %d\n", __func__, i); + return -EINVAL; + } + bL_gic_id[cpu][cluster] = gic_id; + pr_info("GIC ID for CPU %u cluster %u is %u\n", + cpu, cluster, gic_id); + /* * We keep only those logical CPUs which number * is equal to their physical CPU number. This is diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 6bd5a8c1aa..0b6b8bf5df 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -668,6 +668,27 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) #ifdef CONFIG_BL_SWITCHER /* + * gic_get_cpu_id - get the CPU interface ID for the specified CPU + * + * @cpu: the logical CPU number to get the GIC ID for. + * + * Return the CPU interface ID for the given logical CPU number, + * or -1 if the CPU number is too large or the interface ID is + * unknown (more than one bit set). + */ +int gic_get_cpu_id(unsigned int cpu) +{ + unsigned int cpu_bit; + + if (cpu >= NR_GIC_CPU_IF) + return -1; + cpu_bit = gic_cpu_map[cpu]; + if (cpu_bit & (cpu_bit - 1)) + return -1; + return __ffs(cpu_bit); +} + +/* * gic_migrate_target - migrate IRQs to another PU interface * * @new_cpu_id: the CPU target ID to migrate IRQs to diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 40bfcac959..2d7d47e8df 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -75,6 +75,7 @@ static inline void gic_init(unsigned int nr, int start, gic_init_bases(nr, start, dist, cpu, 0, NULL); } +int gic_get_cpu_id(unsigned int cpu); void gic_migrate_target(unsigned int new_cpu_id); #endif /* __ASSEMBLY */