From patchwork Sat Jun 8 14:47:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 17696 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f71.google.com (mail-ee0-f71.google.com [74.125.83.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 6795A2390C for ; Sat, 8 Jun 2013 14:48:14 +0000 (UTC) Received: by mail-ee0-f71.google.com with SMTP id e52sf3004916eek.10 for ; Sat, 08 Jun 2013 07:48:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=PSA3jocQgmIjCFK8lEmq1jwK7PrQAAXF/qYMtiMQ80U=; b=jvSY8/OR0HPjc2pAg5FlCGGcp59+XUFHyNFBb54Jdy3GRQF+MEiepnTOV0sfduJmll GhRs8KK2/QluqmMP686dHmDx/infHXQo91KMonhMB42csX8sAYtirLqy8Y5tEiB5Cs3Z 5KXiR0dSrdTyWCoIsqWY6v0ovRZBzM3Q4OpyoNFPHtyWMViurYzSxGKJd02MrtSZiVyD 1dT7LHQx0diORvM01Jt4CIXL+apFNYYZ9LiWJ6b/ID2XFe2WLWL2Z091lc+U+Fu9EOBG iduosz1okPAzJf70Oc7wS/u7JZ56eHTqtG8C07w4wGEVNfCt3liYgZqtg7nBPy5Pk1dj 0sxw== X-Received: by 10.180.76.115 with SMTP id j19mr753764wiw.2.1370702893602; Sat, 08 Jun 2013 07:48:13 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.181.13.44 with SMTP id ev12ls484542wid.1.gmail; Sat, 08 Jun 2013 07:48:13 -0700 (PDT) X-Received: by 10.194.219.198 with SMTP id pq6mr1718788wjc.58.1370702893516; Sat, 08 Jun 2013 07:48:13 -0700 (PDT) Received: from mail-ve0-x22f.google.com (mail-ve0-x22f.google.com [2607:f8b0:400c:c01::22f]) by mx.google.com with ESMTPS id ek7si817910wid.23.2013.06.08.07.48.13 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 08 Jun 2013 07:48:13 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400c:c01::22f is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c01::22f; Received: by mail-ve0-f175.google.com with SMTP id da11so3709438veb.6 for ; Sat, 08 Jun 2013 07:48:12 -0700 (PDT) X-Received: by 10.58.173.36 with SMTP id bh4mr1668014vec.9.1370702892427; Sat, 08 Jun 2013 07:48:12 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.10.206 with SMTP id pb14csp15994vcb; Sat, 8 Jun 2013 07:48:11 -0700 (PDT) X-Received: by 10.68.170.68 with SMTP id ak4mr3008315pbc.211.1370702891415; Sat, 08 Jun 2013 07:48:11 -0700 (PDT) Received: from mail-pb0-x22d.google.com (mail-pb0-x22d.google.com [2607:f8b0:400e:c01::22d]) by mx.google.com with ESMTPS id ya3si3735226pab.226.2013.06.08.07.48.11 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 08 Jun 2013 07:48:11 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400e:c01::22d is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) client-ip=2607:f8b0:400e:c01::22d; Received: by mail-pb0-f45.google.com with SMTP id mc8so5772355pbc.18 for ; Sat, 08 Jun 2013 07:48:11 -0700 (PDT) X-Received: by 10.68.108.163 with SMTP id hl3mr3040493pbb.160.1370702891039; Sat, 08 Jun 2013 07:48:11 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id rn7sm3320951pbc.12.2013.06.08.07.47.58 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 08 Jun 2013 07:48:10 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, john.stultz@linaro.org, mturquette@linaro.org, heiko@sntech.de Cc: patches@linaro.org, Haojian Zhuang Subject: [PATCH v4 2/7] clk: divider: add CLK_DIVIDER_HIWORD_MASK flag Date: Sat, 8 Jun 2013 22:47:18 +0800 Message-Id: <1370702843-27172-3-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> References: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQkm5NhRGCk+HkwTdlnleEcgSVZgM9moMgefPN8MGtcWrODNXpTzUvqyhHwAu+p0Yh+OaJIo X-Original-Sender: haojian.zhuang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::22f is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner Signed-off-by: Haojian Zhuang --- drivers/clk/clk-divider.c | 15 +++++++++++++-- include/linux/clk-provider.h | 5 +++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 6d96741..ce5cfe9 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -217,8 +217,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->lock) spin_lock_irqsave(divider->lock, flags); - val = readl(divider->reg); - val &= ~(div_mask(divider) << divider->shift); + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + val = div_mask(divider) << (divider->shift + 16); + } else { + val = readl(divider->reg); + val &= ~(div_mask(divider) << divider->shift); + } val |= value << divider->shift; writel(val, divider->reg); @@ -245,6 +249,13 @@ static struct clk *_register_divider(struct device *dev, const char *name, struct clk *clk; struct clk_init_data init; + if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { + if (width + shift > 16) { + pr_warn("divider value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + /* allocate the divider */ div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); if (!div) { diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index fecef88..8e45fd9 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -257,6 +257,10 @@ struct clk_div_table { * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). + * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit + * of this register, and mask of divider bits are in higher 16-bit of this + * register. While setting the divider bits, higher 16-bit should also be + * updated to indicate changing divider bits. */ struct clk_divider { struct clk_hw hw; @@ -271,6 +275,7 @@ struct clk_divider { #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) extern const struct clk_ops clk_divider_ops; struct clk *clk_register_divider(struct device *dev, const char *name,