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Sat, 08 Jun 2013 07:47:57 -0700 (PDT) X-Received: by 10.68.176.197 with SMTP id ck5mr3002278pbc.165.1370702877430; Sat, 08 Jun 2013 07:47:57 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id rn7sm3320951pbc.12.2013.06.08.07.47.47 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 08 Jun 2013 07:47:56 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, john.stultz@linaro.org, mturquette@linaro.org, heiko@sntech.de Cc: patches@linaro.org, Haojian Zhuang Subject: [PATCH v4 1/7] clk: mux: add CLK_MUX_HIWORD_MASK Date: Sat, 8 Jun 2013 22:47:17 +0800 Message-Id: <1370702843-27172-2-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> References: <1370702843-27172-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQlb58jgZDOV4ZxP3+8s0PugsR+Qcc0BP4XncHA8TOwgl1DNJn90dH2JiWD9WECcKp6OYmus X-Original-Sender: haojian.zhuang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::236 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by: Heiko Stuebner Signed-off-by: Haojian Zhuang --- drivers/clk/clk-mux.c | 17 +++++++++++++++-- include/linux/clk-provider.h | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 25b1734..614444c 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -86,8 +86,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) if (mux->lock) spin_lock_irqsave(mux->lock, flags); - val = readl(mux->reg); - val &= ~(mux->mask << mux->shift); + if (mux->flags & CLK_MUX_HIWORD_MASK) { + val = mux->mask << (mux->shift + 16); + } else { + val = readl(mux->reg); + val &= ~(mux->mask << mux->shift); + } val |= index << mux->shift; writel(val, mux->reg); @@ -111,6 +115,15 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, struct clk_mux *mux; struct clk *clk; struct clk_init_data init; + u8 width = 0; + + if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { + width = fls(mask) - ffs(mask) + 1; + if (width + shift > 16) { + pr_err("mux value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } /* allocate the mux */ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 1186098..fecef88 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -299,6 +299,10 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, * Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) + * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this + * register, and mask of mux bits are in higher 16-bit of this register. + * While setting the mux bits, higher 16-bit should also be updated to + * indicate changing mux bits. */ struct clk_mux { struct clk_hw hw; @@ -312,6 +316,7 @@ struct clk_mux { #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) +#define CLK_MUX_HIWORD_MASK BIT(2) extern const struct clk_ops clk_mux_ops;