From patchwork Thu May 9 05:53:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 16803 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-gg0-f199.google.com (mail-gg0-f199.google.com [209.85.161.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id BD2A625E09 for ; Thu, 9 May 2013 05:55:06 +0000 (UTC) Received: by mail-gg0-f199.google.com with SMTP id q1sf2769350gge.10 for ; Wed, 08 May 2013 22:54:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:mime-version:x-beenthere:x-received:received-spf :x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=E8B62BHC/Vrq+KzOZz5RWGHXbFo8+BdJDC85dbgBK2w=; b=FvCGwJaaF46nTWTT1M8YfXIR6UFC8rsdbBpCCsMEyFlSzmP7O1mK/8tqbT2BiERoV9 nzcwFd915Ex66MaLqZYePS4teXgwhX2uLzF2knjsSn6zu4fmHs8BO4z0GunZSBEJB0IV P7z1HhGrCjrUvWjQj6zeHbXZolc8ycpW7m1ozl2Oys5yhe4SaRxIILTn0ez7ASYh7Yq6 1fNel/6yvVAUTNz5yd0JmX2GMHWk5oqfN98dXqmh4sLcz6WsF/iyAufMnwjK9eDBc26X FxgIHaU8dzKymjBSmUAKmCc4MU13FrvW0/Zg1H2/nYe+t1FxCgZnPvRQNO+QlE05cekx unmw== X-Received: by 10.236.132.228 with SMTP id o64mr1060550yhi.45.1368078883587; Wed, 08 May 2013 22:54:43 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.74.66 with SMTP id r2ls1370775qev.48.gmail; Wed, 08 May 2013 22:54:43 -0700 (PDT) X-Received: by 10.58.50.198 with SMTP id e6mr6918755veo.30.1368078883357; Wed, 08 May 2013 22:54:43 -0700 (PDT) Received: from mail-vc0-f175.google.com (mail-vc0-f175.google.com [209.85.220.175]) by mx.google.com with ESMTPS id s9si877103vco.39.2013.05.08.22.54.43 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 May 2013 22:54:43 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.175; Received: by mail-vc0-f175.google.com with SMTP id lf10so2434318vcb.34 for ; Wed, 08 May 2013 22:54:43 -0700 (PDT) X-Received: by 10.52.36.115 with SMTP id p19mr319438vdj.8.1368078883198; Wed, 08 May 2013 22:54:43 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.217.234 with SMTP id pb10csp11443vec; Wed, 8 May 2013 22:54:42 -0700 (PDT) X-Received: by 10.66.72.3 with SMTP id z3mr11373558pau.125.1368078882487; Wed, 08 May 2013 22:54:42 -0700 (PDT) Received: from mail-da0-x22b.google.com (mail-da0-x22b.google.com [2607:f8b0:400e:c00::22b]) by mx.google.com with ESMTPS id hr3si1024067pbc.237.2013.05.08.22.54.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 May 2013 22:54:42 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400e:c00::22b is neither permitted nor denied by best guess record for domain of anup.patel@linaro.org) client-ip=2607:f8b0:400e:c00::22b; Received: by mail-da0-f43.google.com with SMTP id u7so1415420dae.2 for ; Wed, 08 May 2013 22:54:42 -0700 (PDT) X-Received: by 10.66.162.229 with SMTP id yd5mr11518704pab.46.1368078881987; Wed, 08 May 2013 22:54:41 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.72.18.82]) by mx.google.com with ESMTPSA id yp2sm2208179pab.10.2013.05.08.22.54.38 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 08 May 2013 22:54:41 -0700 (PDT) From: Anup Patel To: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, patches@linaro.org, marc.zyngier@arm.com, Anup Patel , Pranavkumar Sawargaonkar Subject: [PATCH] arm64: KVM: Add bits for specifying memory type in stage2 PTE Date: Thu, 9 May 2013 11:23:33 +0530 Message-Id: <1368078813-16904-1-git-send-email-anup.patel@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmM/RiyUIUisy+peHfaoByUJSA47MgE05rmMnXOaYIJG6feSnyMM4IdhIT4r3a0fadNBHyY X-Original-Sender: anup.patel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , We cannot use existing stage1 PTE_ATTRINDX() macro for specifying stage2 memory type because stage1 ATTRINDX = PTE[4:2] and stage2 MEMATTR = PTE[5:2]. This patch adds bit definetions for specifying device, noncacheable, writethrough, and writeback memory types in stage2 PTE and also uses it in PAGE_S2 and PAGE_S2_DEVICE. Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar --- arch/arm64/include/asm/pgtable-hwdef.h | 4 ++++ arch/arm64/include/asm/pgtable.h | 6 ++++-- arch/arm64/mm/mmu.c | 9 +++++++++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index c49cd61..555babb 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -73,6 +73,10 @@ */ #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */ #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ +#define PTE_S2_MT_DEVICE (_AT(pteval_t, 0x0) << 2) /* MemAttr[3:0] */ +#define PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */ +#define PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */ +#define PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */ /* * EL2/HYP PTE/PMD definitions diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 43ce724..3003fd0 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -60,6 +60,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define _PAGE_DEFAULT PTE_TYPE_PAGE | PTE_AF extern pgprot_t pgprot_default; +extern pgprot_t pgprot_s2; +extern pgprot_t pgprot_s2_device; #define __pgprot_modify(prot,mask,bits) \ __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) @@ -79,8 +81,8 @@ extern pgprot_t pgprot_default; #define PAGE_HYP _MOD_PROT(pgprot_default, PTE_HYP) #define PAGE_HYP_DEVICE _MOD_PROT(__pgprot(PROT_DEVICE_nGnRE), PTE_HYP) -#define PAGE_S2 _MOD_PROT(pgprot_default, PTE_S2_RDONLY) -#define PAGE_S2_DEVICE __pgprot_modify(__pgprot(PROT_DEVICE_nGnRE), PTE_PXN, PTE_S2_RDWR) +#define PAGE_S2 _MOD_PROT(pgprot_s2, PTE_USER | PTE_S2_RDONLY) +#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, PTE_USER | PTE_S2_RDWR) #define __PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE) #define __PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 70b8cd4..ef26978 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -46,6 +46,12 @@ EXPORT_SYMBOL(empty_zero_page); pgprot_t pgprot_default; EXPORT_SYMBOL(pgprot_default); +pgprot_t pgprot_s2; +EXPORT_SYMBOL(pgprot_s2); + +pgprot_t pgprot_s2_device; +EXPORT_SYMBOL(pgprot_s2_device); + static pmdval_t prot_sect_kernel; struct cachepolicy { @@ -147,6 +153,9 @@ static void __init init_mem_pgprot(void) } pgprot_default = __pgprot(PTE_TYPE_PAGE | PTE_AF | default_pgprot); + + pgprot_s2 = __pgprot(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED | PTE_S2_MT_WRITEBACK); + pgprot_s2_device = __pgprot(PTE_TYPE_PAGE | PTE_AF | PTE_S2_MT_DEVICE); } pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,