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[86.16.136.251]) by mx.google.com with ESMTPSA id o3sm17516019wia.2.2013.05.03.07.34.04 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 03 May 2013 07:34:05 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: arnd@arndb.de, linus.walleij@stericsson.com, srinidhi.kasagar@stericsson.com, Lee Jones , Vinod Koul , Dan Williams , Per Forlin , Rabin Vincent Subject: [PATCH 21/63] dmaengine: ste_dma40: Don't configure runtime configurable setup during allocate Date: Fri, 3 May 2013 15:32:07 +0100 Message-Id: <1367591569-32197-22-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1367591569-32197-1-git-send-email-lee.jones@linaro.org> References: <1367591569-32197-1-git-send-email-lee.jones@linaro.org> X-Gm-Message-State: ALoCoQndMbyJ2sUxi4L4nBWLA50qCzJwbGgfWGAJCHMdtAwSRa2HgocBZVXDJIm+3sIsPrxUr0qt X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::232 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Using the dmaengine API, allocating and configuring a channel are two separate actions. Here we're removing logical channel configuration from the channel allocating routines. Cc: Vinod Koul Cc: Dan Williams Cc: Per Forlin Cc: Rabin Vincent Signed-off-by: Lee Jones --- drivers/dma/ste_dma40.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 8bff463..34e0fb0 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -2024,6 +2024,9 @@ static int d40_config_memcpy(struct d40_chan *d40c) d40c->dma_cfg = dma40_memcpy_conf_log; d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id]; + d40_log_cfg(&d40c->dma_cfg, + &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); + } else if (dma_has_cap(DMA_MEMCPY, cap) && dma_has_cap(DMA_SLAVE, cap)) { d40c->dma_cfg = dma40_memcpy_conf_phy; @@ -2448,9 +2451,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan) d40_set_prio_realtime(d40c); if (chan_is_logical(d40c)) { - d40_log_cfg(&d40c->dma_cfg, - &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); - if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) d40c->lcpa = d40c->base->lcpa_base + d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;