From patchwork Mon Feb 11 17:10:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 14753 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 719D523DEA for ; Mon, 11 Feb 2013 17:12:36 +0000 (UTC) Received: from mail-ve0-f180.google.com (mail-ve0-f180.google.com [209.85.128.180]) by fiordland.canonical.com (Postfix) with ESMTP id 00AF8A19245 for ; Mon, 11 Feb 2013 17:12:35 +0000 (UTC) Received: by mail-ve0-f180.google.com with SMTP id jx10so5359792veb.11 for ; Mon, 11 Feb 2013 09:12:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=lnOhQhn/K0luQ6NROVctxGIFl8lXaUH2UDpBGZUL+hQ=; b=mF1rkyK3TfkpmNpPjPoFUDUDNlC3qbkVJgYqMkl/rWtZ4u43KpoWItPFvDkjtedX/F /g2koBb0/SpcHV/9W4ptI6C7an/SaKojqbGKYHzRAadLBsO1yYcMKkocrTrQWfhTwJvL qPw6UMtK6KrMrzckmLRRmfkhcgHyCq4cPHKOteHnbnqtYfOjCUBWb7Y2h5F/pcGBy+Tt yj2xVRFL2U7wFM6Pq2NhH62jtu+uxcrDrugMc27FJhdaJFOXKcGB0hgeXzN0ZCbACoh4 inNn+Q05cAtfjEtSKvjACK0uWLVFGNc5owqebvO3FekFxgjG1s5bz5Zr1m0Oj2742HjD uHVg== X-Received: by 10.58.213.37 with SMTP id np5mr2179603vec.54.1360602752148; Mon, 11 Feb 2013 09:12:32 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.252.8 with SMTP id zo8csp108065vec; Mon, 11 Feb 2013 09:12:31 -0800 (PST) X-Received: by 10.50.12.201 with SMTP id a9mr13048638igc.10.1360602751249; Mon, 11 Feb 2013 09:12:31 -0800 (PST) Received: from mail-da0-f43.google.com (mail-da0-f43.google.com [209.85.210.43]) by mx.google.com with ESMTPS id x6si50573799pay.64.2013.02.11.09.12.30 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 11 Feb 2013 09:12:31 -0800 (PST) Received-SPF: neutral (google.com: 209.85.210.43 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) client-ip=209.85.210.43; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.43 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) smtp.mail=haojian.zhuang@linaro.org Received: by mail-da0-f43.google.com with SMTP id u36so2763241dak.2 for ; Mon, 11 Feb 2013 09:12:30 -0800 (PST) X-Received: by 10.66.82.67 with SMTP id g3mr42325995pay.58.1360602750626; Mon, 11 Feb 2013 09:12:30 -0800 (PST) Received: from localhost.localdomain ([27.115.121.35]) by mx.google.com with ESMTPS id m3sm67935973pav.4.2013.02.11.09.12.16 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 11 Feb 2013 09:12:29 -0800 (PST) From: Haojian Zhuang To: shiraz.hashim@st.com, shiraz.linux.kernel@gmail.com, linux@arm.linux.org.uk, tony@atomide.com, linux-arm-kernel@lists.infradead.org, swarren@nvidia.com, grant.likely@secretlab.ca, linus.walleij@linaro.org Cc: patches@linaro.org, Haojian Zhuang Subject: [PATCH v8 12/12] document: devicetree: bind pinconf with pin single Date: Tue, 12 Feb 2013 01:10:59 +0800 Message-Id: <1360602659-4774-13-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1360602659-4774-1-git-send-email-haojian.zhuang@linaro.org> References: <1360602659-4774-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQk8b59iXZC+4OThWnIqKKBaS4HpjNCL3TXEgnuWR9B4RabulfPsxZfcFapb9H6Z9/dI3Pcv From: Haojian Zhuang Add comments with pinconf & gpio range in the document of pinctrl-single. Signed-off-by: Haojian Zhuang Acked-by: Tony Lindgren --- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 118 +++++++++++++++++++- 1 file changed, 117 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 2c81e45..ac63d87 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -1,7 +1,9 @@ One-register-per-pin type device tree based pinctrl driver Required properties: -- compatible : "pinctrl-single" +- compatible : "pinctrl-single" or "pinconf-single". + "pinctrl-single" means that pinconf isn't supported. + "pinconf-single" means that generic pinconf is supported. - reg : offset and length of the register set for the mux registers @@ -14,9 +16,72 @@ Optional properties: - pinctrl-single,function-off : function off mode for disabled state if available and same for all registers; if not specified, disabling of pin functions is ignored + - pinctrl-single,bit-per-mux : boolean to indicate that one register controls more than one pin +- pinctrl-single,drive-strength : array of value that are used to configure + drive strength in the pinmux register. They're value of drive strength + current and drive strength mask. + + /* drive strength current, mask */ + pinctrl-single,power-source = <0x30 0xf0>; + +- pinctrl-single,bias-pullup : array of value that are used to configure the + input bias pullup in the pinmux register. + + /* input, enabled pullup bits, disabled pullup bits, mask */ + pinctrl-single,bias-pullup = <0 1 0 1>; + +- pinctrl-single,bias-pulldown : array of value that are used to configure the + input bias pulldown in the pinmux register. + + /* input, enabled pulldown bits, disabled pulldown bits, mask */ + pinctrl-single,bias-pulldown = <2 2 0 2>; + +- pinctrl-single,bias-autopull : array of value that are used to configure the + input bias autopull. + + /* input, enabled autopull bits, disabled autopull bits, mask */ + pinctrl-single,bias-autopull = <1 1 0 1>; + + bias-pullup & bias-pulldown should be used together without bias-autoupll, + vice visa. + + * Only one bit to control input bias enable or disable: User should use + pinctrl-single,bias-autoupll property at here. + * Two bits to control input bias pullup and pulldown: User should use + pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means + pullup, and the other one bit means pulldown. + * Three bits to control input bias enable, pullup and pulldown. User should + use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias + enable bit should be included in pullup or pulldown bits. + * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as + pinctrl-single,bias-disable. Because pinctrl single driver could implement + it by calling pulldown, pullup, autopull disabled. + +- pinctrl-single,input-schmitt : array of value that are used to configure + input schmitt in the pinmux register. In some silicons, there're two input + schmitt value (rising-edge & falling-edge) in the pinmux register. + + /* input schmitt value, mask */ + pinctrl-single,input-schmitt = <0x30 0x70>; + +- pinctrl-single,input-schmitt-enable : array of value that are used to + configure input schmitt enable or disable in the pinmux register. + + /* input, enable bits, disable bits, mask */ + pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; + +- pinctrl-single,gpio-range : list of value that are used to configure a GPIO + range. They're value of subnode phandle, pin base in pinctrl device, pin + number in this range, GPIO function value of this GPIO range. + The number of parameters is depend on #pinctrl-single,gpio-range-cells + property. + + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>; + This driver assumes that there is only one register for each pin (unless the pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory. @@ -42,6 +107,20 @@ Where 0xdc is the offset from the pinctrl register base address for the device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to be used when applying this change to the register. + +Optional sub-node: In case some pins could be configured as GPIO in the pinmux +register, those pins could be defined as a GPIO range. This sub-node is required +by pinctrl-single,gpio-range property. + +Required properties in sub-node: +- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in + pinctrl-single,gpio-range property. + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + Example: /* SoC common file */ @@ -76,6 +155,29 @@ control_devconf0: pinmux@48002274 { pinctrl-single,function-mask = <0x5F>; }; +/* third controller instance for pins in gpio domain */ +pmx_gpio: pinmux@d401e000 { + compatible = "pinconf-single"; + reg = <0xd401e000 0x0330>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + + /* sparse GPIO range could be supported */ + pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 + &range 12 1 0 &range 13 29 1 + &range 43 1 0 &range 44 49 1 + &range 94 1 1 &range 96 2 1>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; +}; + + /* board specific .dts file */ &pmx_core { @@ -96,6 +198,15 @@ control_devconf0: pinmux@48002274 { >; }; + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x208 0 /* UART0_RXD (IOCFG138) */ + 0x20c 0 /* UART0_TXD (IOCFG139) */ + >; + pinctrl-single,bias-pulldown = <0 2 2>; + pinctrl-single,bias-pullup = <0 1 1>; + }; + /* map uart2 pins */ uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < @@ -122,6 +233,11 @@ control_devconf0: pinmux@48002274 { }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>;