From patchwork Sun Feb 3 10:15:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 14436 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5916023E2E for ; Sun, 3 Feb 2013 10:17:22 +0000 (UTC) Received: from mail-vc0-f177.google.com (mail-vc0-f177.google.com [209.85.220.177]) by fiordland.canonical.com (Postfix) with ESMTP id 02208A18412 for ; Sun, 3 Feb 2013 10:17:21 +0000 (UTC) Received: by mail-vc0-f177.google.com with SMTP id m18so3309002vcm.22 for ; Sun, 03 Feb 2013 02:17:21 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=0MnzLjAXsX2KMXRgc3lIaOK6oQqMFNgqnYWhuHJaU3w=; b=HLGlW45p8LRBvEPrzGdHkCwn8N6YnNTo5jMmotP3HXfhVx2j18tcLMdTdB4ZWVn1i6 NmhMErAV7pn/8+g+Bxk0jgLvP12TvyTU/VQCgekGZm75e1fvAKaSG4rSPnJ0i1fbCHvn lOoxNuddd6rZ+NC5LgrvXCTOdKkEJVPIQvMhWyoMgtRpSGrCnxg0im70bc3UVQgj9b7j 2IPQnFqsPmRAvE8mMc1yU8zHGDcE5hXYolM373RGska6hz/yrU+eVuj55g8Xi18OlxMe u9miz/uD084Wi7DPlpy2HGPoXBwdTOt7b56Z91rHS2WR/SwrLnDv51VBTCigGSZ1jpGb f4NQ== X-Received: by 10.52.66.14 with SMTP id b14mr15614832vdt.0.1359886641492; Sun, 03 Feb 2013 02:17:21 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.252.8 with SMTP id zo8csp40381vec; Sun, 3 Feb 2013 02:17:20 -0800 (PST) X-Received: by 10.66.75.136 with SMTP id c8mr1837184paw.25.1359886640527; Sun, 03 Feb 2013 02:17:20 -0800 (PST) Received: from mail-da0-f45.google.com (mail-da0-f45.google.com [209.85.210.45]) by mx.google.com with ESMTPS id d8si7671354paw.245.2013.02.03.02.17.20 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 03 Feb 2013 02:17:20 -0800 (PST) Received-SPF: neutral (google.com: 209.85.210.45 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) client-ip=209.85.210.45; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.45 is neither permitted nor denied by best guess record for domain of haojian.zhuang@linaro.org) smtp.mail=haojian.zhuang@linaro.org Received: by mail-da0-f45.google.com with SMTP id w4so2273506dam.32 for ; Sun, 03 Feb 2013 02:17:20 -0800 (PST) X-Received: by 10.66.73.164 with SMTP id m4mr43421418pav.12.1359886640126; Sun, 03 Feb 2013 02:17:20 -0800 (PST) Received: from haojian-E6230.domain ([67.198.145.34]) by mx.google.com with ESMTPS id ov4sm14344348pbb.45.2013.02.03.02.17.11 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 03 Feb 2013 02:17:19 -0800 (PST) From: Haojian Zhuang To: linux@arm.linux.org.uk, marek.vasut@gmail.com, robert.jarzmik@free.fr, daniel@caiaq.de, linux-arm-kernel@lists.infradead.org, linus.walleij@linaro.org, grant.likely@secretlab.ca, cxie4@marvell.com, grinberg@compulab.co.il Cc: patches@linaro.org, Haojian Zhuang Subject: [PATCH v2 03/10] gpio: pxa: use platform data for gpio inverted Date: Sun, 3 Feb 2013 18:15:44 +0800 Message-Id: <1359886551-20950-4-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1359886551-20950-1-git-send-email-haojian.zhuang@linaro.org> References: <1359886551-20950-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQm33NruQlVhDTukF1uThwFocegsStdCoY3BC9PCfZu6KC4wP9Vjjy2jwwO1JfvRYt/EpGDa Avoid to judge whether gpio is inverted by identifying cpu in gpio driver. Move this into platform data of gpio driver. Signed-off-by: Haojian Zhuang Tested-by: Igor Grinberg --- arch/arm/mach-pxa/pxa25x.c | 3 +++ drivers/gpio/gpio-pxa.c | 40 +++++++++++++++++++++++++--------------- include/linux/gpio-pxa.h | 1 + 3 files changed, 29 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index f4c293a..66dafb7 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -340,6 +340,9 @@ void __init pxa25x_map_io(void) } static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = { +#ifdef CONFIG_CPU_PXA26x + .inverted = true, +#endif .gpio_set_wake = gpio_set_wake, }; diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 2310665..1f8dfc8 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -71,6 +71,7 @@ struct pxa_gpio_chip { struct gpio_chip chip; void __iomem *regbase; unsigned int irq_base; + bool inverted; char label[10]; unsigned long irq_mask; @@ -126,9 +127,9 @@ static inline int gpio_is_mmp_type(int type) /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, * as well as their Alternate Function value being '1' for GPIO in GAFRx. */ -static inline int __gpio_is_inverted(int gpio) +static inline int __gpio_is_inverted(struct pxa_gpio_chip *chip, int gpio) { - if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) + if ((chip->inverted) && (gpio > 85)) return 1; return 0; } @@ -139,15 +140,13 @@ static inline int __gpio_is_inverted(int gpio) * is attributed as "occupied" here (I know this terminology isn't * accurate, you are welcome to propose a better one :-) */ -static inline int __gpio_is_occupied(unsigned gpio) +static inline int __gpio_is_occupied(struct pxa_gpio_chip *chip, unsigned gpio) { - struct pxa_gpio_chip *pxachip; void __iomem *base; unsigned long gafr = 0, gpdr = 0; int ret, af = 0, dir = 0; - pxachip = gpio_to_pxachip(gpio); - base = gpio_chip_base(&pxachip->chip); + base = gpio_chip_base(&chip->chip); gpdr = readl_relaxed(base + GPDR_OFFSET); switch (gpio_type) { @@ -158,7 +157,7 @@ static inline int __gpio_is_occupied(unsigned gpio) af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; dir = gpdr & GPIO_bit(gpio); - if (__gpio_is_inverted(gpio)) + if (__gpio_is_inverted(chip, gpio)) ret = (af != 1) || (dir == 0); else ret = (af != 0) || (dir != 0); @@ -188,16 +187,19 @@ int pxa_irq_to_gpio(struct irq_data *d) return gpio; } -static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +static int pxa_gpio_direction_input(struct gpio_chip *gc, unsigned offset) { - void __iomem *base = gpio_chip_base(chip); + struct pxa_gpio_chip *chip = NULL; + void __iomem *base = gpio_chip_base(gc); uint32_t value, mask = 1 << offset; unsigned long flags; + chip = container_of(gc, struct pxa_gpio_chip, chip); + spin_lock_irqsave(&gpio_lock, flags); value = readl_relaxed(base + GPDR_OFFSET); - if (__gpio_is_inverted(chip->base + offset)) + if (__gpio_is_inverted(chip, gc->base + offset)) value |= mask; else value &= ~mask; @@ -207,19 +209,22 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) return 0; } -static int pxa_gpio_direction_output(struct gpio_chip *chip, +static int pxa_gpio_direction_output(struct gpio_chip *gc, unsigned offset, int value) { - void __iomem *base = gpio_chip_base(chip); + struct pxa_gpio_chip *chip = NULL; + void __iomem *base = gpio_chip_base(gc); uint32_t tmp, mask = 1 << offset; unsigned long flags; + chip = container_of(gc, struct pxa_gpio_chip, chip); + writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); spin_lock_irqsave(&gpio_lock, flags); tmp = readl_relaxed(base + GPDR_OFFSET); - if (__gpio_is_inverted(chip->base + offset)) + if (__gpio_is_inverted(chip, gc->base + offset)) tmp &= ~mask; else tmp |= mask; @@ -288,7 +293,7 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) return 0; - if (__gpio_is_occupied(gpio)) + if (__gpio_is_occupied(c, gpio)) return 0; type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; @@ -296,7 +301,7 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); - if (__gpio_is_inverted(gpio)) + if (__gpio_is_inverted(c, gpio)) writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); else writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); @@ -474,6 +479,9 @@ static int pxa_gpio_probe_dt(struct platform_device *pdev) return -ENOMEM; if (of_find_property(np, "marvell,gpio-ed-mask", NULL)) pdata->ed_mask = true; + /* It's only valid for PXA26x */ + if (of_find_property(np, "marvell,gpio-inverted", NULL)) + pdata->inverted = true; /* set the platform data */ pdev->dev.platform_data = pdata; gpio_type = (int)of_id->data; @@ -616,6 +624,8 @@ static int pxa_gpio_probe(struct platform_device *pdev) /* unmask GPIO edge detect for AP side */ if (info->ed_mask) writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); + /* update for gpio inverted */ + c->inverted = info->inverted; } if (!use_of) { diff --git a/include/linux/gpio-pxa.h b/include/linux/gpio-pxa.h index 49120b8..0c212a1 100644 --- a/include/linux/gpio-pxa.h +++ b/include/linux/gpio-pxa.h @@ -17,6 +17,7 @@ extern int pxa_irq_to_gpio(struct irq_data *d); struct pxa_gpio_platform_data { bool ed_mask; /* true means that ed_mask reg is available */ + bool inverted; /* only valid for PXA26x */ int (*gpio_set_wake)(unsigned int gpio, unsigned int on); };