From patchwork Wed Dec 12 09:37:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 13492 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2EC494C17AA for ; Wed, 12 Dec 2012 10:24:04 +0000 (UTC) Received: from mail-ie0-f182.google.com (mail-ie0-f182.google.com [209.85.223.182]) by fiordland.canonical.com (Postfix) with ESMTP id CAEC6A18A42 for ; Wed, 12 Dec 2012 10:24:03 +0000 (UTC) Received: by mail-ie0-f182.google.com with SMTP id s9so1653054iec.27 for ; Wed, 12 Dec 2012 02:24:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :resent-from:resent-date:resent-message-id:resent-to:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=zMO+C6QXIHN4f2/7eGyobMU9pCSUNmebA8639RQx/1Q=; b=Bh0lBnOmwlKl1UZHbpNP7yeJI4T7e2N1MzRMr05t8Va3Z8L60iogMGfHpI2OAARtEG LxIQLciaZ1uSbUT/OChXEB3wEExGHu9a/45rEIsyjIVftDUh3jzsTSqhtzUZo4WTDmYw vX8j0vfATe4PauU2RJQo9FYaPK6ttst/EWAOY1UM0+riJmeFHpCzkOv1uuKrLKzT5WP4 S5CGHxMkdmK54QfaJ0Du81RrHhE0O+qioEGO3rMoE6qn+vpwCEOwOK7SfV3dvdEFYEE7 a8SrMH3hfDq3bXJ3icCLx4pf4XkA+u0BPjmKzPYJxo9j0tjTvKYFan40wjFeeu49Ivgg DSww== Received: by 10.50.213.69 with SMTP id nq5mr5526175igc.70.1355307843270; Wed, 12 Dec 2012 02:24:03 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp190081igt; Wed, 12 Dec 2012 02:24:02 -0800 (PST) Received: by 10.14.205.198 with SMTP id j46mr1562687eeo.27.1355307841581; Wed, 12 Dec 2012 02:24:01 -0800 (PST) Received: from mail-ee0-f41.google.com (mail-ee0-f41.google.com [74.125.83.41]) by mx.google.com with ESMTPS id j49si62202655eep.9.2012.12.12.02.24.00 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 12 Dec 2012 02:24:01 -0800 (PST) Received-SPF: neutral (google.com: 74.125.83.41 is neither permitted nor denied by best guess record for domain of fabio.baltieri@linaro.org) client-ip=74.125.83.41; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.83.41 is neither permitted nor denied by best guess record for domain of fabio.baltieri@linaro.org) smtp.mail=fabio.baltieri@linaro.org Received: by mail-ee0-f41.google.com with SMTP id d41so309362eek.0 for ; Wed, 12 Dec 2012 02:24:00 -0800 (PST) Received: by 10.14.0.71 with SMTP id 47mr1542526eea.19.1355307840615; Wed, 12 Dec 2012 02:24:00 -0800 (PST) Received: from localhost ([2a01:2003:1:1d66:8e70:5aff:feac:ad8]) by mx.google.com with ESMTPS id b2sm55031538eep.9.2012.12.12.02.23.59 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 12 Dec 2012 02:24:00 -0800 (PST) Resent-From: Fabio Baltieri Resent-Date: Wed, 12 Dec 2012 11:23:52 +0100 Resent-Message-ID: <20121212102352.GB10536@balto.lan> Resent-To: patches@linaro.org Received: from localhost ([2a01:2003:1:1d66:8e70:5aff:feac:ad8]) by mx.google.com with ESMTPS id 46sm54818151eeg.4.2012.12.12.01.38.10 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 12 Dec 2012 01:38:11 -0800 (PST) From: Fabio Baltieri To: Linus Walleij , Srinidhi Kasagar Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Narayanan G , Fabio Baltieri Subject: [PATCH 1/7] dmaengine: ste_dma40: reset priority bit for logical channels Date: Wed, 12 Dec 2012 10:37:15 +0100 Message-Id: <1355305041-2338-2-git-send-email-fabio.baltieri@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1355305041-2338-1-git-send-email-fabio.baltieri@linaro.org> References: <1355305041-2338-1-git-send-email-fabio.baltieri@linaro.org> X-Gm-Message-State: ALoCoQldGN0rW/bk+mXsZune2+LVo8g7uTIkCl+2P0Sortn61ij29XzK0n4yBL+ctdhiFiFc0qEk From: Narayanan G This patch sets the SSCFG/SDCFG bit[7] PRI only for physical channel requests with high priority. For logical channels, this bit will be zero. Signed-off-by: Narayanan G Reviewed-by: Rabin Vincent Acked-by: Linus Walleij Signed-off-by: Fabio Baltieri --- drivers/dma/ste_dma40_ll.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c index cad9e1d..536e848 100644 --- a/drivers/dma/ste_dma40_ll.c +++ b/drivers/dma/ste_dma40_ll.c @@ -102,17 +102,18 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS; dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS; + /* Set the priority bit to high for the physical channel */ + if (cfg->high_priority) { + src |= 1 << D40_SREG_CFG_PRI_POS; + dst |= 1 << D40_SREG_CFG_PRI_POS; + } + } else { /* Logical channel */ dst |= 1 << D40_SREG_CFG_LOG_GIM_POS; src |= 1 << D40_SREG_CFG_LOG_GIM_POS; } - if (cfg->high_priority) { - src |= 1 << D40_SREG_CFG_PRI_POS; - dst |= 1 << D40_SREG_CFG_PRI_POS; - } - if (cfg->src_info.big_endian) src |= 1 << D40_SREG_CFG_LBE_POS; if (cfg->dst_info.big_endian)