From patchwork Tue Nov 27 13:51:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 13239 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D296023E17 for ; Tue, 27 Nov 2012 13:52:18 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 6BE28A19868 for ; Tue, 27 Nov 2012 13:52:18 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id c10so6396283ieb.11 for ; Tue, 27 Nov 2012 05:52:17 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=62hcjynojhIQbyWlks6KSieq/ri8JcqGkK8NCH1ZN4Y=; b=WAMdDS6PkhYEbaIc+I/F7ZkYFBJoG2ZAs9MY+1m3yClchUqXDDHAS8X80eMf9IQ8J0 WhZSb4R0eHZL0orCGETKRGnZ1leUzmmtnCwPt3N24rRrU8HtkkGrwmFcopkR4h7RMzOZ FU4qi15h1B2viIM2WYJs8pBaCOAh9FIcEnDCFTB9ccGgJ+dL5LmdQYPgs12N1k68+/GY CKlGB6kb8eSRsbyS/uWwLbwUu/AkGldED4mOJ+mshSHiFWhcM/r9ZMNCa84CdPT7180W FXdER+LYc7N8mSAnpMnoJkH/fwo496T3Vt7wj5Ag3v6iCzlpuHP8+G3Iez1w5sMJc5AG 3euQ== Received: by 10.50.152.137 with SMTP id uy9mr15328713igb.62.1354024337894; Tue, 27 Nov 2012 05:52:17 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp460953igt; Tue, 27 Nov 2012 05:52:17 -0800 (PST) Received: by 10.216.197.157 with SMTP id t29mr5697204wen.165.1354024336400; Tue, 27 Nov 2012 05:52:16 -0800 (PST) Received: from eu1sys200aog113.obsmtp.com (eu1sys200aog113.obsmtp.com [207.126.144.135]) by mx.google.com with SMTP id s42si14588707eem.70.2012.11.27.05.52.03 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 27 Nov 2012 05:52:16 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.135; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob113.postini.com ([207.126.147.11]) with SMTP ID DSNKULTFgygnjnxAH1OXwwupTd1OOzb2RxbJ@postini.com; Tue, 27 Nov 2012 13:52:16 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 87206A4; Tue, 27 Nov 2012 13:43:48 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id CAAB7DAD; Tue, 27 Nov 2012 13:51:58 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 2CAE924C2E5; Tue, 27 Nov 2012 14:51:51 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 27 Nov 2012 14:51:57 +0100 From: Linus Walleij To: , Mike Turquette , Mike Turquette Cc: Lee Jones , Anmar Oueja , Linus Walleij , Ulf Hansson , Philippe Begnic , Per Forlin Subject: [PATCH] clk: ux500: assume PRCC clocks are off by default Date: Tue, 27 Nov 2012 14:51:50 +0100 Message-ID: <1354024310-22021-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQl1WmeUtoybzSOrFW/VP7t27zX8z04nrVlmoq0Wuph6lId/B7TPLdPl0QLXQRHAbktwjrDQ From: Linus Walleij The code for the PRCC clock assumed that on boot all the PRCC clocks were on, defining them as enabled. However some such clocks like the clock for the GPIO block 6 in the PER2 peripheral group are not on at all. This would manifest itself as a GPIO block seeming to be clocked and working from the debugfs point of view when actually it was not clocked at all. So instead assume that the PRCC clocks are *not* on, and everything starts working. This may cause a few extra writes to the enable registers but it's worth it. We cannot read the status registers to find out if the clock is on at this point as that means we first have to turn on the clock to the peripheral cluster. Reported-by: Lee Jones Cc: Ulf Hansson Cc: Philippe Begnic Cc: Per Forlin Signed-off-by: Linus Walleij --- Mike: this needs to go into v3.7. (Yes, sorry for not seeing this earlier, but the problem did manifest itself in very strange ways.) If v3.7 is not possible, make sure to add the Cc: stable@kernel.org tag to it. --- drivers/clk/ux500/clk-prcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c index 7eee7f7..0a20a06 100644 --- a/drivers/clk/ux500/clk-prcc.c +++ b/drivers/clk/ux500/clk-prcc.c @@ -120,7 +120,7 @@ static struct clk *clk_reg_prcc(const char *name, goto free_clk; clk->cg_sel = cg_sel; - clk->is_enabled = 1; + clk->is_enabled = 0; clk_prcc_init.name = name; clk_prcc_init.ops = clk_prcc_ops;