From patchwork Tue Nov 6 13:15:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 12687 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A825F23E00 for ; Tue, 6 Nov 2012 13:16:01 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 5994BA19BEA for ; Tue, 6 Nov 2012 13:16:01 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so490428iej.11 for ; Tue, 06 Nov 2012 05:16:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=j6sVo4c0ki+UVLmWufPLbpb2/Or9tt8My1+uKV2HW40=; b=IPhZ6dJ0B9c3cDjdlqaRwUNn7KtrbfoJjtHtkXHZKcKrb6TX5by8yQUFsScaMBrsIe 3I/GXCYTNyWtIz5p/Z0V5/UBESlxaezoYByiwnmZH+ZpZzm7IHdWkF7uXEc/M5nbSfyK N2nx4CZHmIV4y9cZcIbPhTnjq55O565QaG4XedqIxaeCDq79Dy2Bg7gqKgY2QqmtrOMX pw9jY8HbZzWwQHqipIAZr7GCEOBlyXAXz42vDco2MduRqLy5vxVbu8mdb7dmRCWQJM9F WCFJJunOZECbeHydAXJUTDkbNCmwO8hJWInFLjQ1Akzr0oX4Dzst9OI8GReJQnoSWo0O 8wvw== Received: by 10.50.88.233 with SMTP id bj9mr818655igb.70.1352207761142; Tue, 06 Nov 2012 05:16:01 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp39755igt; Tue, 6 Nov 2012 05:16:00 -0800 (PST) Received: by 10.14.182.5 with SMTP id n5mr3621219eem.5.1352207760124; Tue, 06 Nov 2012 05:16:00 -0800 (PST) Received: from eu1sys200aog118.obsmtp.com (eu1sys200aog118.obsmtp.com [207.126.144.145]) by mx.google.com with SMTP id k8si15593930eed.96.2012.11.06.05.15.56 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 06 Nov 2012 05:16:00 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.145 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.145; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.145 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob118.postini.com ([207.126.147.11]) with SMTP ID DSNKUJkNjDKiy9ptwK8pc3OFGyQKCOxWintg@postini.com; Tue, 06 Nov 2012 13:15:59 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id D920844; Tue, 6 Nov 2012 13:15:20 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id A78844A; Tue, 6 Nov 2012 08:33:46 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 222BDA807B; Tue, 6 Nov 2012 14:15:49 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 6 Nov 2012 14:15:53 +0100 From: Linus Walleij To: Cc: Anmar Oueja , Patrice Chotard , Linus Walleij Subject: [PATCH 7/9] ARM: ux500: 8500: add pinctrl support for uart1 and uart2 Date: Tue, 6 Nov 2012 14:15:52 +0100 Message-ID: <1352207752-8026-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmuTtVjkB84tT/ig+DUgV/f5Q8l7/yW5q7wdFvQvx6/PvUILrj5Gf+GjD4Jo1lyKL8bDDzi From: Patrice Chotard This adds pin mappings for UART1 and UART2. Signed-off-by: Patrice Chotard Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-pins.c | 34 +++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0009ca2..05102ad 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -71,6 +71,10 @@ BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| PIN_SLPM_PDIS_ENABLED); BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| PIN_SLPM_PDIS_DISABLED); +BIAS(out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE| + PIN_SLPM_PDIS_DISABLED); +BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE| + PIN_SLPM_PDIS_DISABLED); /* We use these to define hog settings that are always done on boot */ #define DB8500_MUX_HOG(group,func) \ @@ -128,7 +132,7 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { * UART0, we do not mux in u0 here. * uart-0 pins gpio configuration should be kept intact to prevent * a glitch in tx line when the tty dev is opened. Later these pins - * are configured to uart mop500_pins_uart0 + * are configured by uart driver */ DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */ DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */ @@ -139,12 +143,18 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { * TODO: is this used on U8500 variants and Snowball really? * The setting on GPIO31 conflicts with magnetometer use on hrefv60 */ - DB8500_MUX_HOG("u2rxtx_c_1", "u2"), - DB8500_MUX_HOG("u2ctsrts_c_1", "u2"), - DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */ - DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */ + /* default state for UART2 */ + DB8500_MUX("u2ctsrts_c_1", "u2", "uart2"), + DB8500_PIN("GPIO31_V3", in_pu, "uart2"), /* CTS */ + DB8500_PIN("GPIO32_V2", out_hi, "uart2"), /* RTS */ + DB8500_MUX("u2rxtx_c_1", "u2", "uart2"), + DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */ + DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */ + /* Sleep state for UART2 */ + DB8500_PIN_SLEEP("GPIO31_V3", in_wkup_pdis, "uart2"), + DB8500_PIN_SLEEP("GPIO32_V2", out_hi_wkup_pdis, "uart2"), + DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"), + DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"), /* * The following pin sets were known as "runtime pins" before being * converted to the pinctrl model. Here we model them as "default" @@ -161,6 +171,13 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"), DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"), DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"), + /* Mux in UART1 after initialization */ + DB8500_MUX("u1rxtx_a_1", "u1", "uart1"), + DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */ + DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */ + /* Sleep state for UART1 */ + DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"), + DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"), /* MSP1 for ALSA codec */ DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"), DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"), @@ -374,11 +391,8 @@ static struct pinctrl_map __initdata mop500_pinmap[] = { DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu), /* Mux in UART1 and set the pull-ups */ DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_MUX_HOG("u1ctsrts_a_1", "u1"), DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */ DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */ - DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */ /* * Runtime stuff: make it possible to mux in the SKE keypad * and bias the pins