From patchwork Mon Oct 22 13:58:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 12407 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5FF5923EF8 for ; Mon, 22 Oct 2012 13:58:34 +0000 (UTC) Received: from mail-ia0-f180.google.com (mail-ia0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 15D47A1998C for ; Mon, 22 Oct 2012 13:58:33 +0000 (UTC) Received: by mail-ia0-f180.google.com with SMTP id f6so1996710iag.11 for ; Mon, 22 Oct 2012 06:58:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:x-gm-message-state; bh=YHD55o1a8Uf3EcHC8ujNcq26VkmW6ZqCFfSaf0YyqZ8=; b=kFvP5oAUzCX85NdNh/m+MduFp3Te6ACqmVGq1UBc5Zg1HkQWxvQm1dhU26q3LXvkrs f8SU2ZHI7pDYT1nWZdLXPOxksPiA1uiuxjV5Ppl5ow1CeY/MaTxafLTUkuMVC0cBDeo5 5fQbt/NbERoJmb9Yx02bdYX2qRQzQa9K+8lBBdK2ZRnqVzTDdBNPY/9apGxot5M/NG3A 81eEPicQx1kJlMsf9HcreaMYz8WoLqjfy/0K30jo3AN9SoaLFOm8Pr2ZBya0Lw3g2X/q SL7mzxHIJkUxs7DfrrBf13QpS6JSIlmFNz+nHTFkoRlUXmwQK3y/TZ4Acpyo+f/e6bEz rbqg== Received: by 10.50.46.226 with SMTP id y2mr9046838igm.62.1350914313842; Mon, 22 Oct 2012 06:58:33 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp237752igt; Mon, 22 Oct 2012 06:58:33 -0700 (PDT) Received: by 10.14.173.67 with SMTP id u43mr12268674eel.27.1350914312804; Mon, 22 Oct 2012 06:58:32 -0700 (PDT) Received: from eu1sys200aog115.obsmtp.com (eu1sys200aog115.obsmtp.com [207.126.144.139]) by mx.google.com with SMTP id v44si6107662een.31.2012.10.22.06.58.24 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 22 Oct 2012 06:58:32 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) client-ip=207.126.144.139; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) smtp.mail=ulf.hansson@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKUIVRALPi7xxX7rT+l5/HnSTOsWIv4A2p@postini.com; Mon, 22 Oct 2012 13:58:32 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 208F3B0; Mon, 22 Oct 2012 13:50:09 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 61A67BEE; Mon, 22 Oct 2012 13:58:21 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 05040A8096; Mon, 22 Oct 2012 15:58:15 +0200 (CEST) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Mon, 22 Oct 2012 15:58:20 +0200 From: Ulf Hansson To: , Mike Turquette , Mike Turquette Cc: Linus Walleij , Lee Jones , Philippe Begnic , Ulf Hansson Subject: [PATCH 5/5] clk: ux500: Register slimbus clock lookups for u8500 Date: Mon, 22 Oct 2012 15:58:01 +0200 Message-ID: <1350914281-1332-6-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1350914281-1332-1-git-send-email-ulf.hansson@stericsson.com> References: <1350914281-1332-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmj2Xb6YIiH1kaOxj2HdQXxVk0GeznLx+Gjt6Mjx2qmw+bJoiC04afgNB+MCY6aDvqv41fT From: Ulf Hansson At the same time the prcc bit for the kclk is corrected to bit 8 instead of 3. Signed-off-by: Ulf Hansson --- drivers/clk/ux500/u8500_clk.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 0aae929..e2c17d1 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -254,6 +254,7 @@ void u8500_clk_init(void) clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE, BIT(8), 0); + clk_register_clkdev(clk, "apb_pclk", "slimbus0"); clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE, BIT(9), 0); @@ -441,8 +442,8 @@ void u8500_clk_init(void) clk_register_clkdev(clk, NULL, "nmk-i2c.2"); clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", - U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE); - /* FIXME: Redefinition of BIT(3). */ + U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE); + clk_register_clkdev(clk, NULL, "slimbus0"); clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);