From patchwork Wed Oct 3 09:22:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 11971 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2016724156 for ; Wed, 3 Oct 2012 09:23:04 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id AFC22A18B31 for ; Wed, 3 Oct 2012 09:23:03 +0000 (UTC) Received: by ieje10 with SMTP id e10so16266120iej.11 for ; Wed, 03 Oct 2012 02:23:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=ScEraWnMsL0/dMneNgfox1ppMYAvI3czLPgeoDAXwtU=; b=CkWmuVd800MN+xhYA1xgMGmtR3dLBq0GKRo7KyW/Z+IjvaU7dnP8//zYIz0M0UvGPu 2ByR2r/Af5BwDBnyEZvcubU75efZuz/PrfjLPB7KPANtyu21vAqKP1BundZnW+H1yYjK yNvS1IKDo3aquMV/qC0SKKZbvjhGoJCDvqgmrr3MhwjJ5tgk+zE14OJPYR5PhCl37XPU oNrgbLBZevuBu9CnCAyO0h/yWrc7cRVpEaB4tgjrtywXnUBA6GrmnHVE4poHIGJzs/nW 5PvvEI6nUBRwyOeSTILOWuoXXAj/tPx3TuWnQ+m4XeATt4W8YhpHRJhB2v1AfLI60FMc G8hQ== Received: by 10.50.160.165 with SMTP id xl5mr11552344igb.0.1349256183122; Wed, 03 Oct 2012 02:23:03 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp129337igc; Wed, 3 Oct 2012 02:23:02 -0700 (PDT) Received: by 10.204.147.153 with SMTP id l25mr253642bkv.109.1349256180993; Wed, 03 Oct 2012 02:23:00 -0700 (PDT) Received: from mail-bk0-f50.google.com (mail-bk0-f50.google.com [209.85.214.50]) by mx.google.com with ESMTPS id gy2si5753577bkc.18.2012.10.03.02.23.00 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 03 Oct 2012 02:23:00 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.214.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=209.85.214.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by bkwq16 with SMTP id q16so6194714bkw.37 for ; Wed, 03 Oct 2012 02:23:00 -0700 (PDT) Received: by 10.204.146.19 with SMTP id f19mr282218bkv.4.1349256180145; Wed, 03 Oct 2012 02:23:00 -0700 (PDT) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id m19sm2846202bkm.8.2012.10.03.02.22.58 (version=SSLv3 cipher=OTHER); Wed, 03 Oct 2012 02:22:59 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Nicolas Pitre , Will Deacon Subject: [PATCH] ARM: proc-v7: Ensure correct instruction set after cpu_reset Date: Wed, 3 Oct 2012 10:22:50 +0100 Message-Id: <1349256170-4367-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-Gm-Message-State: ALoCoQmgXfa4b8pq3DiQiaUEQ5e6/ErQW4dM6+1colRJ3qKldKoQv5wK0XOLDit7Vl6swL791+ce Because mov pc, never switches instruction set when executed in Thumb code, Thumb-2 kernels will silently execute the target code after cpu_reset as Thumb code, even if the passed code pointer denotes ARM (bit 0 clear). This patch uses bx instead, ensuring the correct instruction set for the target code. Thumb code in the kernel is not supported prior to ARMv7, so other CPUs are not affected. Signed-off-by: Dave Martin Acked-by: Will Deacon Acked-by: Nicolas Pitre --- arch/arm/mm/proc-v7.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c2e2b66..ca5b575 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -57,7 +57,7 @@ ENTRY(cpu_v7_reset) THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) mcr p15, 0, r1, c1, c0, 0 @ disable MMU isb - mov pc, r0 + bx r0 ENDPROC(cpu_v7_reset) .popsection