From patchwork Mon Sep 24 14:43:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 11673 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C1C8F23E42 for ; Mon, 24 Sep 2012 14:44:05 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 563FEA18EC4 for ; Mon, 24 Sep 2012 14:44:05 +0000 (UTC) Received: by ieje10 with SMTP id e10so10115588iej.11 for ; Mon, 24 Sep 2012 07:44:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:x-gm-message-state; bh=kt+/sHjgMgWLB5WvOoRZVNniQ4hrKAl/zz1+vc5KNhg=; b=BEh8+8RyTyp7ayYUVScZYfuRx2xske45VQ/rElAEdGnfQzhgBbu7qsbx0DMAn2QS5c WyrFoa0ywDwaY3veGVzC2L6ujNJYoIlQmmmrtlbofyvTIlw8EpOF3iTeouL7R+q4/gCN txvZcdIBk+otIgxRpKMxLX9poajxaIj1tDlg7LKtTnQOdecNxyBRSyMtHh/BJZKHFnL4 ZdU6cpkQ6sFUtCZWTkYMVY/XWZb8B8/JgSZDJGW9WnRsr/s8OUkIc6zL83Y5XoZmpheE 19kZbkzl/ij5K/yfv1VZlA9vZmKw2k6pvAB8Zx6pGQ5Kz5dIqr+XOJjOUUdPdj795tZP Gvyg== Received: by 10.50.184.129 with SMTP id eu1mr5500715igc.0.1348497844738; Mon, 24 Sep 2012 07:44:04 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp246562igc; Mon, 24 Sep 2012 07:44:03 -0700 (PDT) Received: by 10.14.205.9 with SMTP id i9mr3333989eeo.21.1348497843175; Mon, 24 Sep 2012 07:44:03 -0700 (PDT) Received: from eu1sys200aog115.obsmtp.com (eu1sys200aog115.obsmtp.com [207.126.144.139]) by mx.google.com with SMTP id 42si6844352eee.84.2012.09.24.07.43.55 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 24 Sep 2012 07:44:03 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) client-ip=207.126.144.139; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) smtp.mail=ulf.hansson@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKUGBxqwooCjAziVzFzN4GmaYKs5Gtk8u3@postini.com; Mon, 24 Sep 2012 14:44:03 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 48A2B139; Mon, 24 Sep 2012 14:43:36 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1C1C04847; Mon, 24 Sep 2012 14:43:35 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id D22CE24C2F9; Mon, 24 Sep 2012 16:43:22 +0200 (CEST) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Mon, 24 Sep 2012 16:43:30 +0200 From: Ulf Hansson To: , Mike Turquette , Mike Turquette , Cc: Linus Walleij , Lee Jones , Philippe Begnic , Srinidhi Kasagar , Ulf Hansson Subject: [PATCH 2/3] clk: ux500: Support prcmu ape opp voltage clock Date: Mon, 24 Sep 2012 16:43:18 +0200 Message-ID: <1348497799-32143-3-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1348497799-32143-1-git-send-email-ulf.hansson@stericsson.com> References: <1348497799-32143-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmjWu8jgUf3XPQcK/qEaU+WjxC+nVGALqq6nvnqAVptNATf5tNMt3kCB/CB/ucOYgjLdm4r From: Ulf Hansson Some scalable prcmu clocks needs to be handled in conjuction with the ape opp 100 voltage. A new prcmu clock type clk_prcmu_opp_volt_scalable is implemented to handle this. Signed-off-by: Ulf Hansson --- drivers/clk/ux500/clk-prcmu.c | 55 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/ux500/clk.h | 6 +++++ 2 files changed, 61 insertions(+) diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c index 930cdfe..04577ca 100644 --- a/drivers/clk/ux500/clk-prcmu.c +++ b/drivers/clk/ux500/clk-prcmu.c @@ -133,6 +133,40 @@ out_error: hw->init->name); } +static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw) +{ + int err; + struct clk_prcmu *clk = to_clk_prcmu(hw); + + err = prcmu_request_ape_opp_100_voltage(true); + if (err) { + pr_err("clk_prcmu: %s failed to request APE OPP VOLT for %s.\n", + __func__, hw->init->name); + return err; + } + + err = prcmu_request_clock(clk->cg_sel, true); + if (err) + prcmu_request_ape_opp_100_voltage(false); + + return err; +} + +static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw) +{ + struct clk_prcmu *clk = to_clk_prcmu(hw); + + if (prcmu_request_clock(clk->cg_sel, false)) + goto out_error; + if (prcmu_request_ape_opp_100_voltage(false)) + goto out_error; + return; + +out_error: + pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, + hw->init->name); +} + static struct clk_ops clk_prcmu_scalable_ops = { .prepare = clk_prcmu_prepare, .unprepare = clk_prcmu_unprepare, @@ -167,6 +201,17 @@ static struct clk_ops clk_prcmu_opp_gate_ops = { .recalc_rate = clk_prcmu_recalc_rate, }; +static struct clk_ops clk_prcmu_opp_volt_scalable_ops = { + .prepare = clk_prcmu_opp_volt_prepare, + .unprepare = clk_prcmu_opp_volt_unprepare, + .enable = clk_prcmu_enable, + .disable = clk_prcmu_disable, + .is_enabled = clk_prcmu_is_enabled, + .recalc_rate = clk_prcmu_recalc_rate, + .round_rate = clk_prcmu_round_rate, + .set_rate = clk_prcmu_set_rate, +}; + static struct clk *clk_reg_prcmu(const char *name, const char *parent_name, u8 cg_sel, @@ -250,3 +295,13 @@ struct clk *clk_reg_prcmu_opp_gate(const char *name, return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags, &clk_prcmu_opp_gate_ops); } + +struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, + const char *parent_name, + u8 cg_sel, + unsigned long rate, + unsigned long flags) +{ + return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags, + &clk_prcmu_opp_volt_scalable_ops); +} diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h index 836d7d1..f36eeed 100644 --- a/drivers/clk/ux500/clk.h +++ b/drivers/clk/ux500/clk.h @@ -45,4 +45,10 @@ struct clk *clk_reg_prcmu_opp_gate(const char *name, u8 cg_sel, unsigned long flags); +struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, + const char *parent_name, + u8 cg_sel, + unsigned long rate, + unsigned long flags); + #endif /* __UX500_CLK_H */